Dekompozycyjne metody syntezy w projektowaniu systemów cyfrowych dla heterogenicznych struktur programowalnych

Rawski, M.

Artykuł - szczegóły

Tytuł artykułu

Dekompozycyjne metody syntezy w projektowaniu systemów cyfrowych dla heterogenicznych struktur programowalnych

Autorzy

Rawski M.

Identyfikatory

Warianty tytułu

Decomposition-based synthesis methods is digital system designing for heterogeneous programmable structures

Języki publikacji

Abstrakty

Od wielu lat możliwość nowoczesnych technologii mikroelektronicznych w dziedzinie układów scalonych wzrastają znacznie szybciej, niż zdolność projektantów (wspomaganych narzędziami CAD) do ich wykorzystania. Powoduje to konieczność ciągłego doskonalenia metod projektowania i opracowywania nowych narzędzi wspomagających ten proces w taki sposób, aby było możliwe wykorzystanie w jak największym stopniu możliwości nowoczesnej mikroelektronik. W dziedzinie systemów cyfrowych głównym kierunkiem badań obejmuje opracowanie efektywnych metod opisu projektowego układu na poziomie systemu (System Level), które zapewniają ujednolicone modelowanie zarówno jego części sprzętowej, jak i programowej. Należy jednak pamiętać, że ostatecznie – w celu realizacji projektowanego urządzenia cyfrowego – niezbędna jest translacja opisu części sprzętowej z poziomu systemu do poziomu przesłań międzyrejestrowych RTL. Na tym poziomie układ cyfrowy jest reprezentowany jako sieć bloków kombinacyjnych, automatów FSM, rejestrów i struktur, takich jak pamięć RAM, sumatory, układy mnożące itp. Jakość odwzorowania tak reprezentowanego systemu w zasobach logicznych docelowej architektury w ogromnej mierze zależy od efektywności algorytmów zastosowanych na etapie syntezy logicznej. Jest to szczególnie widoczne w przypadku struktur programowalnych FPGA, które dzięki postępowi mikroelektroniki maja obecnie budowę heterogeniczną – składają się z elementów logicznych różnego typu. Niestety, rozwój metod syntezy logicznej nie nadąża za rozwojem układów FPGA. Istniejące algorytmy, oparte na koncepcji dekompozycji funkcjonalnej, nie są w stanie w pełni wykorzystać zalet heterogenicznej budowy nowoczesnych struktur programowalnych. W niniejszej pracy zaprezentowano dekompozycyjne metody syntezy logicznej, umożliwiające efektywne wykorzystanie heterogenicznej struktury nowoczesnych układów FPGA.

For many years possibilities delivered by modern microelectronic technology grow much faster than abilities of designers to utilize them. This necessitates continuous improvement of design methods and development of new tools to assist design process in such a way, that the possibilities of modern microelectronics are utilized I most possible degree. In the area of digital systems the main direction of research includes the development of effective methods of description of the proposed system at a system level, that provides a unified modeling of both the hardware and software. However in order to implement hardware part of the designed digital device the system level description has to be translated to register transfer level (RTL). At this level digital circuit is represented as a network of combinational blocks, FSMs, registers and modules, such as RAMs, adders, multipliers, etc. The quality of mapping of RTL description in the logic resources of target architecture largely depends on the efficiency of the algorithms used in logic synthesis stage. This is particularly evident in the case of FPGA programmable structures which, due to the improvements in microelectronics, have heterogeneous architecture – are built of different types of logic elements. Unfortunately, the development of logic synthesis methods cannot keep up with the development of FPGA devices. Existing algorithms based on the concept of functional decomposition are not able to fully exploit the advantages of heterogeneous architecture of modern programmable structures. Un this work synthesis methods based on functional decomposition concept are presented, that enable the efficient us o heterogeneous structure of modern FPGAs.

Słowa kluczowe

synteza logiczna dekompozycja heteogeniczne układy FPGA

logic synthesis decomposition heterogeneous FPGA devices

Wydawca

Oficyna Wydawnicza Politechniki Warszawskiej

Czasopismo

Prace Naukowe Politechniki Warszawskiej. Elektronika

Rocznik

2013

Tom

z. 191

Strony

5--154

Opis fizyczny

Bibliogr. 172 poz., rys., tab., wykr.

Twórcy

autor

Rawski M.

Wydział Elektroniki i Technik Informacyjnych5-- Politechnika Warszawska

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