Reconfigurable General-purpose Processor Idea Overview

• Autorzy: Zarzycki I
• Języki publikacji: EN

Abstrakty

EN

This paper presents the idea of the reconfigurable general-purpose processor implemented as dynamically reconfigurable FPGA (called “reconfigurable processor” in the rest of this document). Proposed solution is compared with currently available general-purpose processors performing instructions sequentially (called “sequential processors” in the rest of this paper). This document presents the idea of such reconfigurable processor and its operation without going into implementation details and technological limitations. The main novelty of reconfigurable processor lays in lack of typical for other processors sequential execution of instructions. All operations (if only possible) are executed in parallel, in hardware also at subistruction level. Solution proposed in this paper should give speed up and lower power consumption in comparison with other processors currently available. Additionally proposed architecture does not requires neither any modifications in source codes of already existing, portable programs nor any changes in development process. All of the changes can be performed by compiler at the stage of compilation.

Słowa kluczowe

EN

processor; FPGA; dynamic reconfiguration; reconfigurable computing paradigm

PL

procesor rekonfigurowalny; FPGA; bezpośrednio programowalna macierz bramek; rekonfiguracja dynamiczna

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 1
• Strony: 37--42
• Opis fizyczny: Bibliogr. 7 poz.

Twórcy

autor

Zarzycki I

• Department of Microelectronics and Computer Science (DMCS), Lodz University of Technology, Łódź, Poland

Bibliografia

• [1] H. V. J. M. Moreno, A. Villa, A. Napieralski, G. Sassatelli, and E. Lavarec, “Perplexus: Pervasive computing framework for modeling complex virtually-unbounded systems,” Proceedings of the 2007 NASA/ESA Conference on Adaptive Hardware and Systems , pp. 587–591, Aug. 2007.
• [2] L. Zhuo and V. K. Prasanna, “Scalable and modular algorithms for floating-point matrix multiplication on reconfigurable computing systems,” IEEE Transactions on Parallel and Distributed Systems , vol. 18, pp. 433–448, Apr. 2007.
• [3] M. H. Tarek El-Ghazawi, Esam El-Araby, K. Gaj, V. Kindratenko, and D. Buell, “The promise of high-performance reconfigurable computing,” Computer , vol. 41, pp. 69–76, Feb. 2008.
• [4] A. T. Hayden Kwok-Hay So and R. Brodersen, “A unified hardware/software runtime environment for fpga-based reconfigurable computers using borph,” in Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis , 2006, pp. 259–264.
• [5] Y. D. Y. Arcilio J. Virginia and K. L. Bertels, “An empirical comparison of ansi-c to vhdl compilers: Spark, roccc and dwarv,” ProRISC, 18th Annual Workshop on Circuits, System and Signal Processing, Utreht 2007 , pp. 388–394, Nov. 2007.
• [6] D. Jain, “Object oriented programming constructs in vhsic hardware description language ‘why & how’,” Journal of Theoretical and Applied Information Technology , vol. 3, pp. 30–37, Jan. 2007.
• [7] F. W. Wibowo, “Interoperability of reconfiguring system on fpga using a design entry of hardware description language,” Proceedings of International Conference on Advances in Computing, Control, and Telecommunication Technologies 2011 , vol. 2, pp. 79–83, Mar. 2011.