Performance Targeted Synthesis of ASM Controllers on FPGA

• Autorzy: Salauyou V. , Bulatowa I.
• Języki publikacji: EN

Abstrakty

EN

Performance-driven synthesis of controller circuits is very important and challenging task in digital systems design. The clock frequency of a synchronous sequential logic circuit is dependent in a large part on the maximum propagation delay through its combinational block. The paper presents a new method for FPGA-based design of high-speed Algorithmic State Machine (ASM) controllers. The proposed approach is based on the introduction of additional states of the state machine in order to simplify transition and output logical functions to implement them in the single-level structures. The proposed technique is applied at the stage of converting the ASM chart to the finite state machine description and allows obtaining such an HDL specification that provides an increase in the designed system speed. Experimental results show that our approach achieves an average performance gain of 22.24% to 29.72% (for various FPGA devices) compared with the conventional synthesis method.

Słowa kluczowe

EN

Algorithmic State Machine (ASM); ASM chart; finite state machine (FSM); performance optimization

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2018
• Tom: Vol. 64, No. 2
• Strony: 31--33
• Opis fizyczny: Bibliogr. 15 poz., rys., tab., wzory

Twórcy

autor

Salauyou V.

• Bialystok University of Technology, 45A Wiejska St., 15-351 Bialystok, Poland

autor

Bulatowa I.

• Bialystok University of Technology, 45A Wiejska St., 15-351 Bialystok, Poland

Bibliografia

• [1] Clare C.: Designing logic systems using the state machines. McGraw- Hill, New York, 1973.
• [2] Baranov S.: Logic Synthesis for Control Automata. Kluwer Academic Publisher, Boston, 1994.
• [3] Green D. H., Chughtai M. A.: Use of multiplexers in the direct synthesis of ASM-based designs. IEE Proc. E, Comput. & Digital Tech. Vol. 133, No. 4, pp.194–200, 1986.
• [4] Lu J. Y., Kim J. D., Chin S. K.: Hardware composition with hardware flowcharts and process algebras. In: 2nd IEEE International Conference on Engineering of Complex Computer Systems Proceedings, IEEE, Montreal, Canada , pp. 352–364, 1996.
• [5] Baranov S.: Minimization of algorithmic state machines. In: 24th Euromicro Conference Proceedings, IEEE, Vasteras, Sweden, pp. 176–179, 1998.
• [6] De Pablo, S., Cáceres S., Cebrián J. A., Berrocal M.: A proposal for ASM++ diagrams. In: Design and Diagnostics of Electronic Circuits and Systems Proceedings, IEEE, Krakow, Poland, , pp. 1–4, 2007.
• [7] Barkalov A., Titarenko L., Bieganowski J.: Logic Synthesis for Finite State Machines Based on Linear Chains of States. Studies in Systems, Decision and Control, Springer, Berlin, 2018.
• [8] Hertwig A., Wunderlich H.: Fast controllers for data dominated applications. In: European Design and Test Conference (ED & TC '97) Proceedings, IEEE, Paris, France, pp. 84–89, 1997.
• [9] Czerwinski R., Kania D.: State Assignment and Optimization of Ultra- High-Speed FSMs Utilizing Tristate Buffers. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, No. 1, Article 3, 2016.
• [10] Kim E., Lee D., Saito H., Nakamura H., Lee J., Nanya T.: Performance optimization of synchronous control units for datapaths with variable delay arithmetic units. In: ASP-DAC Asia and South Pacific Design Automation Conference Proceedings, IEEE,Kitakyushu, Japan, pp. 816–819, 2003.
• [11] Weng S., Kuo Y., Chang S.: Timing Optimization in Sequential Circuit by Exploiting Clock-Gating Logic ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 17, No. 2, Article 16, 2012.
• [12] Bommu S., O'Neill N., Ciesielski M.: Retiming-based factorization for sequential logic optimization. ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 5, No. 3, pp. 373–398, 2000.
• [13] Huang S.: On speeding up extended finite state machines using catalyst circuitry. In: ASP-DAC 2001 Asia and South Pacific Design Automation Conference (DAC '06) Proceedings, IEEE, Yokohama, Japan, pp. 583–588, 2001.
• [14] Gupta G. R., Gupta M., Panda P. R.: Rapid estimation of control delay from high-level specifications. In: 43rd Design Automation Conference Proceedings, ACM, San Francisco, USA, pp. 455–458, 2010.
• [15] Salauyou V., Klimowicz A., Grzes T., Bulatowa I., Dimitrowa- Grekow T.: Synthesis methods of finite state machines implemented in package ZUBR. In: 6th International Conference Computer-Aided Design of Discrete Devices (CAD DD’7) Proceedings, National Academy of Sciences of Belarus, Minsk, pp. 53–56, 200.

Uwagi

EN

The work was supported by Bialystok University of Technology grant S/WI/3/2018.

PL

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).