Simple anti capacitor open-circuit self-oscillation in a CMOS Schmitt trigger-invertor oscillator circuit for a fail-safe relay drive

• Autorzy: Summatta Chuthong , Deeon Sansak

Identyfikatory

DOI

10.15199/48.2019.03.23

Warianty tytułu

PL

Prosty układ kondensatora zapobiegający samooscylacjom w obwodzie przerzutnika Schmitta w układzie przekształtnika

• Języki publikacji: EN

Abstrakty

EN

Oscillator circuits with a CMOS Schmitt trigger-inverter are commonly used in applications that relate to relay driver circuits. It is possible to devise a fail-dangerous occurrence from the circuit, in which an open fault happens at the input circuit between the capacitor and input inverter IC. The causes of this self-oscillation event contribute to the failure of other parts of the circuit. This paper presents countermeasures for self-oscillation of the capacitor open-circuit self-oscillation in a CMOS Schmitt trigger-invertor oscillator circuit for a fail-safe relay drive. The proposed circuit replaces a normal 2-pin capacitor with a special 4-pin designed capacitor which connects a parallel resistor between the input CMOS inverter and the ground source. This paper carried out experimentation using Failure Modes and Effects Analysis (FMEA).The results showed that the output logic was high when the circuit had an open fault. Thus, the new designed circuit had no fail-dangerous occurrences.

PL

W artykule opisano środki zaracze zapobiegające samooscylacjom w obwodzie pojemnościowym CMOS przerzutnika Schmitta w obwodzie przekształtnika. Metoda poleg ana zastąpieniu dwukońcówkowej pojemności obwodem z czterema końcówkami z rezystorem miedzy wejściem przekształtnika a masą.

Słowa kluczowe

EN

CMOS inverter; self-oscillation; open-fault; fail safe

PL

przekształtnik CMOS; samooscylacja; przerzutnik Schmitta

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2019
• Tom: R. 95, nr 3
• Strony: 97--100
• Opis fizyczny: Bibliogr. 8 poz., rys., tab.

Twórcy

autor

Summatta Chuthong

• Department of Electrical Engineering, Pathumwan Institute of Technology, 833 Rama1 Wangmai District, Bangkok, Thailand

autor

Deeon Sansak

• Department of Electrical Engineering, Pathumwan Institute of Technology, 833 Rama1 Wangmai District, Bangkok, Thailand

Bibliografia

• [1] V. Bobin and S. Whitaker, “Design of fail-safe CMOS logic circuits,” VLSI, 1991. Proceedings., First Great Lakes Symposium on, Kalamazoo, MI, USA, Mar., 1991.
• [2] K. Otake, Y. Hirao, T. Fukuda and K. Futsuhara, “A Safety Relay with Contacts in a safe Operational Order and Its Application,” Safety of Industrial Automated Systems SIAS 2010 Conference on, Tampere, Finland, Jun., 2010.
• [3] S. Deeon, Y. Hirao and K. Tanaka, “A Relay Drive Circuit for a Safe Operation Order and its Fail-safe Measures”, Reliability Engineering Association of Japan Journal of, Vol.34, No.7, pp.489-500, 2012.
• [4] S. Deeon and A. Pilikeaw, “Anti Self-oscillation of CMOS Invertors ICs for a Fail-safe Relay Drive Circuit” Electrical Engineering Network of Rajamangala University of Technology 2015 Conference on, Chonburi, Thailand, May., 2015.
• [5] C. Summatta, W. Khamsen, A. Pilikeaw and S. Deeon, “Design and Simulation of Relay Drive Circuit for Safe Operation Order,” Mathematics, Engineering & Industrial Applications 2016 (ICoMEIA 2016) Conference on, Songkhla, Thailand, Aug., 2016.
• [6] Łukasz CHRUSZCZYK, Jerzy RUTKOWSKI, “Tolerance Maximisation in Fault Diagnosis of Analogue Electronic Circuits” PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), ISSN 0033-2097, R. 87 NR 10/2011
• [7] IEC 61800-5-2:2007, adjustable speed electrical power drive systems -- Part 5-2: Safety requirements -- Functional.
• [8] S. Deeon, Y. Hirao and K. Futsuhara, “A Fail-safe Counter and its Application to Low-speed Detection”, Transactions of Reliability Engineering Association of Japan, Vol.33, No.3, pp.135-144, 2011.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).