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FPGA Implementation of Neural Nets

Treść / Zawartość
Identyfikatory
Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The field programmable gate array (FPGA) is used to build an artificial neural network in hardware. Architecture for a digital system is devised to execute a feed-forward multilayer neural network. ANN and CNN are very commonly used architectures. Verilog is utilized to describe the designed architecture. For the computation of certain tasks, a neural network’s distributed architecture structure makes it potentially efficient. The same features make neural nets suitable for application in VLSI technology. For the hardware of a neural network, a single neuron must be effectively implemented (NN). Reprogrammable computer systems based on FPGAs are useful for hardware implementations of neural networks.
Rocznik
Strony
599--604
Opis fizyczny
Bibliogr. 31 poz., rys., tab., wykr.
Twórcy
  • Sri Jayachamarajendra College of Engineering, JSS Science and Technology University, Mysore, India
  • Sri Jayachamarajendra College of Engineering, JSS Science and Technology University, Mysore, India
  • Sri Jayachamarajendra College of Engineering, JSS Science and Technology University, Mysore, India
Bibliografia
  • [1] Jihong Liu, Deqin Liang, “A Survey of FPGA-Based Hardware Implementation of ANNs”, School of Information Science and Engineering Northeastern University, Shenyang-110004, China-2005. Communications, vol. 25, no. 5, pp. 10-15, October 2018, https://doi.org/10.1109/MWC.2018.1800049
  • [2] Shuai Li, Ken Choi, “Artificial Neural Network Implementation in FPGA: A Case Study”, Department of Electrical and Computer Engineering, Illinois Institute of Technology, USA/Yunsik Lee, School of ECE, UNIST, Ulsan, Korea- ISOCC 2016. https://doi.org/10.1109/ISOCC.2016.7799795
  • [3] PDr. Reza Raeisi , Armin Kabir, “Implementation of Artificial Neural Network on FPGA”, Indiana State University, Indiana., American Society for Engineering Education, Illinois-Indiana and North Central Joint Section Conference IPFW (Mar-2006).
  • [4] Esraa Zeki Mohammed and Haitham Kareem Ali, “Hardware Implementation of Artificial Neural Network Using Field Programmable Gate Array”, International Journal of Computer Theory and Engineering, Vol. 5, No. 5, 2013. https://doi.org/10.7763/IJCTE.2013.V5.795
  • [5] Philippe Dondon, Julien Carvalho, R´emi Gardere, Paul Lahalle, Georgi Tsenov and Valeri Mladenov, “Implementation of a Feed-forward Artificial Neural Network in VHDL on FPGA”, 12th Symposium on Neural Network Applications in Electrical Engineering (NEUREL 2014), Mare, Romania (2019).
  • [6] Jihan Zhu and Peter Sutton, “FPGA Implementations of Neural Networks A Survey of a Decade of Progress”, School of Information Technology and Electrical Engineering, The University of Queensland, Brisbane, Queensland 4072, Australia.
  • [7] Marcin Pietras, “Hardware conversion of neural networks simulation models for Neural Processing Accelerator implemented as FPGA-based SoC”, Computer Science and Information Technology West Pomeranian University of Technology, ZUT Szczecin, Poland (2018).
  • [8] Saima Kanwal , Arslan Yousaf , Maria Imtiaz , Jalil Abbas , Arslan Ali, “Survey paper on Advanced Equipment Execution of ANN for FPGA”, Computer Engineering and Intelligent Systems Vol.9, No.7, (2019).
  • [9] S. Oniga, A. Tisan, D. Mic, A. Buchman and A. Vida-Ratiu, “Optimizing FPGA Implementation of FeedForward Neural Networks”, Electronic and Computer Engineering Department, North University, Baia
  • [10] Pedro Ferreira, Pedro Ribeiro, Ana Antunes, and Fernando Morgado Dias, “Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA” - (2018).
  • [11] Hardik H. Makwana , Dharmesh J. Shah , Priyesh P. Gandhi, “FPGA Implementation of Artificial Neural Network”, International Journal of Emerging Technology and Advanced Engineering (2004).
  • [12] Suhap Sahin, Yasar Becerikli, and Suleyman Yazici , “Neural Network Implementation in Hardware Using FPGAs”, Department of Computer Eng., Kocaeli University, Izmit, Turkey, Vol 12, 2018.
  • [13] Marco Bettoni, Gianvito Urgese, Yuki Kobayashi, Enrico Macii, and Andrea Acquaviva, “A Convolutional Neural Network Fully Implemented on FPGA for Embedded Platforms”, first New Generation of CAS (2017).
  • [14] Yongmei Zhou, Jingfei Jiang, “An FPGA-based Accelerator Implementation for Deep Convolutional Neural Network”, 4th International Conference on Computer Science and Network Technology (ICCSNT 2015).
  • [15] Yasmeen Farouk, Sherine Rady, “Optimizing MRI Registration using Software/Hardware Co-Design Model on FPGA”, International Journal of Innovative Technology and Exploring Engineering, Vol 10, Issue 12 (IJITEE) 2020.
  • [16] Yuchen Yao, Qinghua Duan, Zhiqian Zhang, Jiabao Gao, Jian Wang, Meng Yang, “A FPGA-based Hardware Accelerator for Multiple Convolutional Neural Networks”, State Key Laboratory of ASIC System, Fudan University, Shanghai 2018.
  • [17] Yufeng Hao, “A General Neural Network Hardware Architecture on FPGA”, University of Birmingham, 2018.
  • [18] Fasih Ud Din , Farrukh Tuo Xie Chun, Zhang Zhihua Wang, Fellow, “Optimization for Efficient Hardware Implementation of CNN on FPGA”, IEEE international conference on integrated circuits and technologies and applications (2018).
  • [19] Mohammad Samragh, Mohammad Ghasemzadeh, and Farinaz Koushanfar, “Customizing Neural Networks for Efficient FPGA Implementation”, IEEE 25th Annual International Symposium on Field-Programmable Custom Computing Machines 2018. https://doi.org/10.1109/FCCM.2017.43
  • [20] Dai Rongshi, Tang Yongming , “Accelerator Implementation of Lenet-Convolution Neural Network Based on FPGA with HLS”, 2019 3rd International Conference on Circuits, System and Simulation.
  • [21] Leandro D. Medus, Taras Iakymchuk, Jose V. Frances-Villora, Manuel Bataller-Mompeán, Alfredo Rosado-Muñoz, ”A Novel Systolic Parallel Hardware Architecture for the FPGA Acceleration of Feedforward Neural Networks”, IEEE Access, vol 2920885, 2019. https://doi.org/10.1109/ACCESS.2019.2920885
  • [22] M. Zhu, Q. Kuang, J. Lin, Q. Luo, C. Yang and M. Liu, ”A Z Structure Convolutional Neural Network Implemented by FPGA in Deep Learning,”44th Annual Conference of the IEEE Industrial Electronics Society, pp. 2677-2682, 2018.
  • [23] H. O. Ahmed, M. Ghoneima and M. Dessouky, ”Concurrent MACunit design using VHDL for deep learning networks on FPGA,” IEEE Symposium on Computer Applications Industrial Electronics ISCAIE, pp. 31-36, 2018. https://doi.org/10.1109/ISCAIE.2018.8405440
  • [24] M. Hailesellasie, S. R. Hasan, F. Khalid, F. A. Wad and M. Shafique, ”FPGA-Based Convolutional Neural Network Architecture with Reduced Parameter Requirements,” IEEE International Symposium on Circuits and Systems, pp. 1-5, 2018.
  • [25] L. Bai, Y. Lyu and X. Huang, ”A Unified Hardware Architecture for Convolutions and Deconvolutions in CNN,” IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5,2020.
  • [26] S. -P. Pan, Z. Li, Y. -J. Huang and W. -C. Lin, ”FPGA realization of activation function for neural network,” 7th International Symposium on Next Generation Electronics , pp. 1-2, 2018.
  • [27] Y. -C. Ling, H. -H. Chin, H. -I. Wu and R. -S. Tsay, ”Designing A Compact Convolutional Neural Network Processor on Embedded FPGAs,” IEEE Global Conference on Artificial Intelligence and Internet of Things (GCAIoT), pp. 1-7, 2020.
  • [28] C. Crema et al., ”Embedded platform-based system for early detection of Alzheimer disease through transcranial magnetic stimulation,” IEEE Sensors Applications Symposium (SAS), pp. 1-6, 2018. https://doi.org/10.1109/SAS.2018.8336774
  • [29] S. Ivanov, S. Stankov and T. Nenov, ”FPGA Based Neural Networks for Characters Recognition,” 20th International Symposium on Electrical Apparatus and Technologies (SIELA), pp. 1-3, 2018.
  • [30] Yufei Ma, Yu Cao, Fellow, Sarma Vrudhula, and Jae-sun Seo, ”Optimizing the Convolution Operation to Accelerate Deep Neural Networks on FPGA”, IEEE Transactions On Very Large Scale Integration (Vlsi) Systems,2018. https://doi.org/10.1109/TVLSI.2018.2815603
  • [31] Sachin Nayak, Shweta Vincent, Sumathi K, Om Prakash Kumar, and Sameena Pathan,” An Ensemble of Statistical Metadata and CNN Classification of Class Imbalanced Skin Lesion Data”, Intl Journal of Electronics and Telecommunications, 2022, vol. 68, no. 2, pp. 251-257 https://doi.org/10.24425/ijet.2022.139875
Uwagi
Opracowanie rekordu ze środków MEiN, umowa nr SONP/SP/546092/2022 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2022-2023).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-dd24dd18-cf46-437a-848e-1a0ff2389642
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