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Edge termination design for 1.7 kV silicon carbide p-i-n diodes

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Języki publikacji
EN
Abstrakty
EN
In this work, in order to obtain breakdown voltage values of the 4H-SiC p-i-n diodes above 1.7 kV, three designs have been examined: single-zone junction termination extention (JTE), double-zone JTE and a structure with concentric rings outside each of the areas of the double-zone JTE (space-modulated JTE). The influence of geometry and the level of p-type doping in the JTE area as well as the charge as the interface between the p-type JTE area and the passivation layer on the diode breakdown voltage was studied. The effect of statistical dispersion of drift layer parameters (thickness, doping level) on diodes breakdown voltage with various JTE structures was investigated as well. The obtained results showed that the breakdown volatge values for a diode with single zone JTE are very sensitive both to the dose of JTE area and charge accumulated at the JTE/dielectric interface. The use of a double zone or space-modulated JTE structures allows for obtaining breakdown voltage above 1.7 kV for a much wider range of doping parameters and with better tolerance to positive charge at the JTE/dielectric interface, as well as better tolerance to statistical dispersion of active layer parameters compared to a single zone JTE structure.
Rocznik
Strony
367--375
Opis fizyczny
Bibliogr. 21 poz., rys. tab.
Twórcy
autor
  • Warsaw University of Technology, Institute of of Microelectronics and Optoelectronics, ul. Koszykowa 75, 00-662 Warsaw, Poland
  • Łukasiewicz Research Network – –Institute Electron Technology, al. Lotników 32/46, 02-668 Warsaw, Poland
autor
  • Warsaw University of Technology, Institute of of Microelectronics and Optoelectronics, ul. Koszykowa 75, 00-662 Warsaw, Poland
Bibliografia
  • [1] R.R. Potera and T.J. Han, “Silicon Carbide Diodes in Power-Factor Correction Circuits: Device and Circuit Design Aspects”, IEEE Power Electron. Mag. 6(1), 34–39 (2019).
  • [2] M. Maciążek and M. Pasko, “Optimum allocation of active power filters in large supply systems”, Bull. Pol. Ac.: Tech. 64(1), 37–44 (2016).
  • [3] W. Janke, A. Hapka, and M. Oleksy, “DC characteristics of the SiC Schottky diodes”, Bull. Pol. Ac.: Tech., 59(2) 183–188 (2011).
  • [4] J. Woźny, A. Kovalchuk, Z, Lisik, J. Podgórski, P. Bugalski, A. Kubiak and Ł. Ruta, “DFT simulation of stacking faults defects in 4H-SiC”, 2018 XIV-th International Conference on Perspective Technologies and Methods in MEMS Design (MEM-STECH), Lwów, 65–68 (2018).
  • [5] H.W. Kim, W. Bahng, G.H. Song, S.C. Kim, N.K. Kim, and E.D. Kim, “Edge Termination Technique for SiC Power Devices”, Mater. Sci. Forum 457–460, 1241–1244 (2004).
  • [6] V.A.K. Temple and W. Tantraporn, “Junction termination extension for near-ideal breakdown voltage in p-n junctions”, IEEE Trans. Electron Devices, 33(10), 1601–1608 (1986).
  • [7] A. Mahajan and B.J. Skromme, “Design and optimization of junction termination extension (JTE) for 4H–SiC high voltage Schottky diodes”, Solid-State Electronics 49(6), 945–955 (2005).
  • [8] T. Hiyoshi, T. Hori, J. Suda, and T. Kimoto, “Simulation and Experimental Study on the Junction Termination Structure for High-Voltage 4H-SiC PiN Diodes”, IEEE Trans. Electron Devices 55(8), 1841–1846 (2008).
  • [9] B.J. Baliga, Fundamentals of Power Semiconductor Devices, Springer International Publishing AG, 2019.
  • [10] Y. Huang, Y. Wang, X. Kuang, W. Wang, J. Tang, and Y. Sun, “Step-Double-Zone-JTE for SiC Devices with Increased Tolerance to JTE Dose and Surface Charges”, Micromachines 9(12), 610 (2018).
  • [11] G. Feng, J. Suda, and T. Kimoto, “Space-Modulated Junction Termination Extension for Ultrahigh-Voltage p-i-n Diodes in 4H-SiC”, IEEE Trans. Electron Devices 59(2), 414–418 (2012).
  • [12] H. Niwa, J. Suda, and T. Kimoto, “21.7 kV 4H-SiC PiN Diode with a Space-Modulated Junction Termination Extension”, Appl. Phys. Express 5(6), 064001 (2012).
  • [13] K. Nakayama et al., “27.5 kV 4H-SiC PiN diode with space-modulated JTE and carrier injection control”, 2018 IEEE 30th International Symposium on Power Semiconductor Devices and ICs (ISPSD), 395–398 (2018).
  • [14] V.K. Khanna, Insulated Gate Bipolar Transistor IGBT Theory and Design, IEEE Press, New Jersey, 2003.
  • [15] Silvaco ATLAS User’s Manual (2019).
  • [16] T. Hatakeyama, T. Watanabe, T. Shinohe, K. Kojima, K. Arai and N. Sano, “Impact ionization coefficients of 4H silicon carbide”, Appl. Phys. Lett. 85(8), 1380 (2004).
  • [17] T. Hatakeyama, “Measurements of impact ionization coefficients of electrons and holes in 4H-SiC and their application to device simulation”, Phys. Status Solidi (a), 206(10), 2284–2294 (2009).
  • [18] R. Ghandi et al., “Surface-Passivation Effects on the Performance of 4H-SiC BJTs”, IEEE Trans. Electron Devices 58(1), 259–265 (2011).
  • [19] A. Taube, M. Guziewicz, K. Kosiel, K. Gołaszewska-Malec, K. Król, R. Kruszka, E. Kamińska, and A. Piotrowska, “Characterization of Al2O3 /4H-SiC and Al2 O3 /SiO2/4H-SiC MOS structures”, Bull. Pol. Ac.: Tech. 64(3), 547–551 (2016).
  • [20] K.B. Król, Dielectrics produced by thermal methods in silicon carbide for MOS semiconductor devices, PhD thesis (in Polish), Warsaw University of Technology, Faculty of Electronics and Information Technology, Warsaw (2015).
  • [21] K. Król, M. Sochacki, W. Strupinski, K. Racka, M. Guziewicz, P. Konarski, M. Misnik, and J. Szmidt, “Chlorine-enhanced thermal oxides growth and significant trap density reduction at SiO2/SiC interface by incorporation of phosphorus”, Thin Solid Films, 591(A), 86–89, (2015).
Uwagi
PL
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2020).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-db30b398-98c6-48e0-a6e8-9792f09abf50
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