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Upgraded low voltage analog Current-to-Voltage converter with negative feedback

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Języki publikacji
EN
Abstrakty
EN
In this paper, an improved version of a current to voltage (C-V) converter is proposed. As compared to the previous version, the number of used transistors has been reduced by 1 and equals 7. The main results of this change are: an improvement of the circuit transfer function linearity, reduction the converter input resistance and decrease of the required supply voltage. Improvements in the considered converter results not only from the reduction of the number of the used transistors but also from the proposed realization of the feedback loop. In this way, it was possibly to get a strong loop gain. As a results, the achieved minimum supply voltage has been reduces from 2V, in case of the previous published converter version, to as low level as 1.2 V, in the case of the newly proposed solution. As for the linearity of the C-V transfer function, apart from its strong loop gain, an important role play also output transistors operating in a small drain to source region (linear region). Working in this region, one obtains a quasi linear voltage to current relationship. The theoretical and simulation results are in a good agreement and are promising.
Twórcy
autor
  • Faculty of Telecommunication, Computer Science & Electrical Engineering, University of Technology and Life Sciences, Bydgoszcz, Poland
Bibliografia
  • [1] J. Milman, C. C. Halkias, "Electronic Devices and Circuits", Mc Graw-Hill, New York, 1967.
  • [2] E. Vittoz, „Micropower techniques" in design of analog-digital VLSI circuits for telecommunications and signal processing", Edit. J. Franca and Y. Tsividis, Prentice Hall, 1993.
  • [3] Chi-Tsong Chen, "Linear System Theory and Design", Oxford University Press, Inc. New York, NY, USA ©1995.
  • [4] B. Pellegrini, "Improved feedback theory", IEEE Transactions on Circuits and Systems I: Regular Papers, Volume: 56, Issue: 9, Sept. 2009.
  • [5] M. Schiarmann, R. L.Geiger, "Simple CMOS Transresistor", Electronics Letters, Vol. 37, Issue 23. pp. 1386-1387, 2001.
  • [6] R. Długosz, T. Talaśka, W. Pedrycz, R. Wojtyna, "Realization of the Conscience Mechanism in CMOS Implementation of Winner-Takes-All Self-Organizing Neural Networks", IEEE Trans. Neural Networks, Vol. 21, No. 6, pp.961-971,2010.
  • [7] R. Wojtyna, „Analog-technique-based neuroprocessing implemented in hardware", IEEE Workshop SPA 2009 (Signal Processing - Algorithms, Architectures, Arrangements and Applications), pp. 9-12, 2009.
  • [8] R. Wojtyna, T. Talaśka, "Transresistance CMOS neuron for adaptive neural networks implemented in hardware", Bulletin of the Polish Academy of Sciences, Technical Sciences, Vol. 54, No. 4, pp. 443-448, 2006.
  • [9] R. Wojtyna, "Low-voltage Quasi-linear Current-to-Voltage Analog Signal Processing", International Conference MIXDES'2016, pp. 585-588, Łódź, 2016.
  • [10] R. Wojtyna, "Versatile Low-Output-Resistance Low-Voltage Current-to-Voltage Analog Converter", International Journal of Microelectronics and Computer Science", pp. 73-78, Vol. 7, No. 2, 2016.
  • [11] R. Wojtyna, "Applying Negative Feedback to Improve Linearity and Input Property of Analog CMOS Transresistor", International Conference MIXDES'2017, pp. 79-83, Łódź, 2017.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-da0791e9-b57f-4bed-aea5-f0fdbbe61604
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