Optimization problems in the synthesis of multiple-valued logic networks

• Autorzy: Deniziak S. , Wiśniewski M. , Kurczyna K.
• Języki publikacji: EN

Abstrakty

EN

The paper discusses some aspects of FPGA-oriented synthesis of multiple-valued logic (MVL) network, i.e. a network of modules connected by multiple-valued signals. MVL networks are built during high-level synthesis, as a source specification of logical systems or during re-synthesis of gate-level circuits. FPGA-oriented synthesis of MVL is based on decomposing modules into smaller ones, each fitting in one logic cell. In this paper, we show that the order, according to which the modules are decomposed, has a great influence on the efficiency of the synthesis. This paper presents the case study which demonstrates the above problem as well as some experimental results and conclusions.

Słowa kluczowe

EN

multiple-valued logic network; symbolic decomposition; FPGA; logic synthesis

• Wydawca: Wydawnictwo PAK
• Czasopismo: Measurement Automation Monitoring
• Rocznik: 2016
• Tom: Vol. 62, No. 5
• Strony: 166--168
• Opis fizyczny: Bibliogr. 13 poz., rys., tab., schem.

Twórcy

autor

Deniziak S.

• Department of Information Systems, Kielce University of Technology, Poland 7 Tysiaclecia PP Ave., 25-314 Kielce, Poland

autor

Wiśniewski M.

• Department of Information Systems, Kielce University of Technology, Poland 7 Tysiaclecia PP Ave., 25-314 Kielce, Poland

autor

Kurczyna K.

• Department of Information Systems, Kielce University of Technology, Poland 7 Tysiaclecia PP Ave., 25-314 Kielce, Poland

Bibliografia

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