SoC-FPGA based concept of hardware aided quantum simulation

• Autorzy: Długopolski Jacek , Czerski Jakub , Knapik Mateusz

Identyfikatory

DOI

10.14313/JAMRIS/2‐2024/9

• Języki publikacji: EN

Abstrakty

EN

Contemporary industry and science expectations towards technological solutions set the bar high. Current approaches to increasing the computing power of standard systems are reaching the limits of physics known to humankind. Fast, programmable systems with relatively low power consumption are a different concept for performing complex calculations. Highly parallel processing opens up a number of possibilities in the context of accelerating calculations. Application of SoC (System On Chip) with FPGA (Field- Programmable Gate Array) enables the delegating of a part of computations to the gates matrix, thereby expediting processing by using parallelization of hardware operations. This paper presents the general concept of using SoC FPGA systems to support the CPU (Central Processing Unit) in many modern tasks. While some tasks might be really hard to implement on an FPGA in a reasonable time, the SoC FPGA platform allows for easy low-level interconnections, and with such virtualized access to the hardware computing resources, it is seen as making FPGAs, or hardware in general, more accessible to engineers accustomed to high-level solutions. The concept presented in the article takes into account the limited resources of cheaper educational platforms, which, however, still provide an interesting and alternative hybrid solution to the problem of parallelization and acceleration of data processing. This allows encountered limitations to be overcome and the flexibility known from high-level solutions and high performance achieved with low-level programming to be maintained without the need for a high financial background.

Słowa kluczowe

EN

FPGA; SoC; quantum circuit; parallel computing; web service; accelerating calculations

• Wydawca: Łukasiewicz Industrial Research Institute for Automation and Measurements PIAP
• Czasopismo: Journal of Automation Mobile Robotics and Intelligent Systems
• Rocznik: 2024
• Tom: Vol. 18, No. 2
• Strony: 17--23
• Opis fizyczny: Bibliogr. 14 poz., rys.

Twórcy

autor

Długopolski Jacek

• Faculty of Computer Science, AGH University of Krakow, al. A. Mickiewicza 30, 30-059 Kraków, Poland

• https://orcid.org/0000-0003-2139-0469

autor

Czerski Jakub

• European Organization for Nuclear Research CERN, Espl. des Particules 1, 1211 Meyrin, Switzerland

autor

Knapik Mateusz

• CyberOwl Ltd, No 1 Colmore Square, Birmingham, United Kingdom, B4 6AA

Bibliografia

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• [7] M. C. Herbordt, Y. Gu, T. VanCourt, J. Model, B. Sukhwani, and M. Chiu, “Computing modelsfor fpga‐based accelerators”, Computing in Science Engineering, vol. 10, no. 6, 2008, 35–45. doi: 10.1109/MCSE.2008.143.
• [8] S. Hoover, “Hardware accelerated web applications using cloud fpgas”, 2018.
• [9] Z. Jiang, N. Audsley, D. Shill, K. Yang, N. Fisher, and Z. Dong, “Brief industry paper: Axi-interconnectrt: Towards a real-time axi-interconnect for system-on-chips”. In: 2021 IEEE 27th Real-Time and Embedded Technology and Applications Symposium (RTAS), 2021, 437–440. doi: 10.1109/RTAS52030.2021.00046.
• [10] M. Levental, “Tensor networks for simulating quantum circuits on fpgas”, 2021.
• [11] X. Li, C. Fei, and D. Maskell, “Fpga overlays: Hardware‐based computing for the masses”, 2018. doi: 10.15224/978‐1‐63248‐144‐3‐12.
• [12] S. Mittal, “A survey of fpga‐based accelerators for convolutional neural networks”, Neural Computing and Applications, vol. 32, 2020. doi: 10.1007/s00521‐018‐3761‐1.
• [13] R. Skhiri, V. Fresse, J. Jamont, B. Suffran, and J. Malek, “From fpga to support cloud to cloud of fpga: State of the art”, International Journal of Reconfigurable Computing, vol. 2019, 2019, 1–17. doi: 10.1155/2019/8085461.
• [14] A. Wicaksana, “Portable infrastructure for heterogeneous reconϐigurable devices in a cloud‐fpga environment”, 2018.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki (2025).