Simulation framework and thorough analysis of the impact of barrier lowering on the current in SB-MOSFETs

• Autorzy: Schwarz M. , Calvet L. E. , Snyde J. P. , Krauss T. , Schwalke U. , Kloes A.
• Języki publikacji: EN

Abstrakty

EN

In this paper we present a simulation framework to account for the Schottky barrier lowering models in SBMOSFETs within the Synopsys TCAD Sentaurus tool-chain. The improved Schottky barrier lowering model for field emission is considered. A strategy to extract the different current components and thus accurately predict the on- and off-current regions are adressed. Detailed investigations of these components are presented along with an improved Schottky barrier lowering model for field emission. Finally, a comparison for the transfer characteristics is shown for simulation and experimental data.

Słowa kluczowe

EN

2D Poisson equation; device modeling; double-gate MOSFET; field emission; framework; Schottky barrier; Synopsys; TCAD; thermionic emission; thermionic current; tunneling current

PL

równanie Poissona dwuwymiarowe; modelowanie elementów elektronicznych; tranzystor MOS dwubramkowy; emisja polowa; framework; bariera Schottky'ego; Synopsys; TCAD; emisja termoelektronowa; prąd termoelektronowy; prąd tunelowy

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2017
• Tom: Vol. 8, nr 2
• Strony: 72--79
• Opis fizyczny: Bibliogr. 25 poz., rys., wykr.

Twórcy

autor

Schwarz M.

• Robert Bosch GmbH, Germany

autor

Calvet L. E.

• Université Paris-Sud, France

autor

Snyde J. P.

• JCap, LLC, USA

autor

Krauss T.

• Technische Universität Darmstadt, Germany

autor

Schwalke U.

• Technische Universität Darmstadt, Germany

autor

Kloes A.

• Technische Hochschule Mittelhessen, Germany

Bibliografia

• [1] J. Bruner, ”Intel 22nm 3-D Tri-Gate Transistor Technology”, News release and press materials (Intel), http://www.intel.com, 2011.
• [2] Q. Liu, et al., ”High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond”, IEDM, Washington DC, USA, 2013.
• [3] J. M. Larson, J. P. Snyder, ”Overview and status of metal S/D Schottkybarrier MOSFET technology”, IEEE Transaction Electron Devices 53 (5), 1048–1058, 2006.
• [4] W. E. Purches, A. Rossi, R. Zhao, S. Kafanov, T. L. Duty, A. S. Dzurak, S. Rogge, and G. C. Tettamanzi, ”A planar Al-Si Schottky barrier metal-oxide-semiconductor field effect transistor operated at cryogenic temepratures”, Applied Physics Letters 107, 2015.
• [5] J. P. Snyder, ”Benefits of Schottky Barrier MOS vs. Conventional Doped S/D MOS”, Meeting on Schottky Barrier devices, Ueberherrn, Germany, 2016.
• [6] S. M. Sze, Kwog K. Ng, ”Physics of Semiconductor Devices”, John Wiley & Sons, 2007.
• [7] L. E. Calvet, ”Electrical Transport in Schottky Barrier MOSFETs”, PhD Thesis, Yale University, USA, 2001.
• [8] L. E. Calvet, H. Luebben, M. A. Reed, C. Wang, J. P. Snyder, J. R. Tucker, ”Suppression of leakage current in Schottky barrier metal–oxide–semiconductor field-effect transistors”, Journal of Applied Physics 91 (2), 757–759, 2002.
• [9] R. A. Vega, ”Comparison study of tunneling models for Schottky field effect transistors and the effect of Schottky barrier lowering”, IEEE Transaction Electron Devices 53 (7), 1593–1600, 2006.
• [10] J. L. Padilla, L. Knoll, F. Gámiz, Q. T. Zhao, A. Godoy, and S. Mantl, ”Simulation of Fabricated 20-nm Schottky Barrier MOSFETs on SOI: Impact of Barrier Lowering”, IEEE Transaction Electron Devices 59 (5), 1320–1327, 2012.
• [11] ”ATLAS User’s Manual”, SILVACO, Inc., 2010.
• [12] R. A. Vega, and Tsu-Jae King Liu, ”A Comparative Study of Dopant-Segregated Schottky and Raised Source/Drain Double-Gate MOSFETs”, IEEE Transaction Electron Devices 55 (10), 2665–2677, 2008.
• [13] M. Schwarz, L. E. Calvet, J. P. Snyder, T. Krauss, U. Schwalke, and A. Kloes, ”On the Physical Behavior of Cryogenic IV and III-V Schottky Barrier MOSFET Devices”, IEEE Transaction Electron Devices 64 (9), 3808–3815, 2017.
• [14] ”TCAD Sentaurus”, Synopsys, Inc., c-2016.12 Edition, 2016.
• [15] A. Schenk and S. M¨uller, ”Analytical Model of the Metal-Semiconductor Contact for Device Simulation”, Simulation of Semiconductor Devices and Processes (SISDEP) 5, 441–444, 1993.
• [16] A. Schenk, ”Advanced Physical Models for Silicon Device Simulation”, Springer, 1998.
• [17] H. A. Bethe, ”Theory of Boundary Layer of Crystal Rectifiers”, MIT Radiat. Lab. Rep., 1942.
• [18] A. Schenk and G. Heiser, ”Modeling and simulation of tunneling through ultra-thin gate dielectrics”, Applied Physics Letters 81 (12), 7900–7908, 1997.
• [19] M. Ieong, P. M. Solomon, S.E. Laux, H.-S. P. Wong, D. Chidambarrao, ”Comparison of Raised and Schottky Source/Drain MOSFETs Using a Novel Tunneling Contact Model”, IEDM, 733–736, 1998.
• [20] G. Wentzel, ”Eine Verallgemeinerung der Quantenbedingungen für Würfel Zwecke der Wellenmechanik”, Z. Physik 38, 518–529, 1926.
• [21] H. A. Kramers, ”Wellenmechanik und halbzahlige Quantisierung”, Z. Physik 39, 828–840, 1926.
• [22] L. Brillouin, La mécanique ondulatoire de Schrödinger; ”une Méthode Générale de resolution durchschnittliche Näherungswerte successives”, Comptes rendus (Paris) 138, 24–26, 1926.
• [23] J. G. Simmons, ”Generalized Formula for the Electric Tunnel Effect between Similar Electrodes Separated by a Thin Insulating Film”, Journal of Applied Physics 34 (6), 1963.
• [24] L. Hutin, M. Vinet, T. Poiroux, C. Le Royer, B. Previtali, C. Vizioz, D. Lafond, Y. Morand, M. Rivoire, F. Nemouchi, V. Carron, T. Billon, S. Deleonibus, O. Faynot, ”Dual Metallic Source and Drain Integration on Planar Single and Double Gate SOI CMOS down to 20nm: Performance and Scalability Assessment”, IEDM, 1–4, December, 2009.
• [25] L. Hutin, ”Study of Schottky Barrier MOSFETs on SOI, SiGeOI and GeOI Substrates”, PhD Thesis, University of Grenoble, France, 2010.

Uwagi

Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).