A new architecture of thermometer to binary code encoder for 4 - bit FLASH ADC in 45nm CMOS process

• Autorzy: Sam D.S.Shylu , Paul P. Sam , Reddy Golamari Kiran Kumar , Manideep Nagothu , Venkatesh Nethikuntla Chakali , Manideep Pulikonda Durga Sai

Identyfikatory

DOI

10.15199/48.2023.11.32

Warianty tytułu

PL

Nowa architektura termometru do enkodera kodu binarnego dla 4-bitowego FLASH ADC w procesie 45nm CMOS

• Języki publikacji: EN

Abstrakty

EN

In this work, a new architecture of Thermometer to Binary Encoder is designed in 45nm CMOS Technology for 4-bit FLASH ADC. The Thermometer code is converted to intermediate gray code and then to binary code in the proposed encoder. The 4-bit FLASH ADC is integrated with the proposed low –power encoder, Double-tail Dynamic Comparator and resistive ladder networks. Simulation results show that the proposed encoder consumes 119μW power with 1V supply voltage. The 4-bit FLASH ADC consumes less power when compared with the conventional ADCs.

PL

W tej pracy zaprojektowano nową architekturę termometru do kodera binarnego w technologii 45nm CMOS dla 4-bitowego FLASH ADC. Kod termometru jest konwertowany na pośredni kod Graya, a następnie na kod binarny w proponowanym enkoderze. 4-bitowy FLASH ADC jest zintegrowany z proponowanym koderem małej mocy, dwustronnym komparatorem dynamicznym i rezystancyjnymi sieciami drabinkowymi. Wyniki symulacji pokazują, że proponowany enkoder pobiera moc 119μW przy napięciu zasilania 1V. 4-bitowy FLASH ADC zużywa mniej energii w porównaniu z konwencjonalnymi przetwornikami ADC.

Słowa kluczowe

EN

thermometer-code encoder; comparator; flash ADC; low power

PL

termometr-kod enkoder; komparator; flash ADC; mała moc

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2023
• Tom: R. 99, nr 11
• Strony: 188--191
• Opis fizyczny: Bibliogr. 20 poz., rys., tab.

Twórcy

autor

Sam D.S.Shylu

• Department of Electronics and Communication Engineering, Karunya Institute of Technology and Sciences

• https://orcid.org/0000-0001-5559-0202

autor

Paul P. Sam

• Department of Mechanical Engineering, Karunya Institute of Technology and Sciences

autor

Reddy Golamari Kiran Kumar

• UG Scholar, Karunya Institute of Technology and Sciences

autor

Manideep Nagothu

• UG Scholar, Karunya Institute of Technology and Sciences

autor

Venkatesh Nethikuntla Chakali

• UG Scholar, Karunya Institute of Technology and Sciences

autor

Manideep Pulikonda Durga Sai

• UG Scholar, Karunya Institute of Technology and Sciences

Bibliografia

• 1. M. Pavan Kumar, P. Venkatesh, K. Venkatesh, G. Chanakya, S. Ravi Teja,Design and implementation of efficient FLASH ADC”, International Journal of Engineering Research & Technology [IJERT],(2020) No.09(05),1116-1119.
• 2. George Tom Varghese, Prof. Dr. Kamalakanta Mahapatra., A Low Power Reconfigurable Encoder for Flash ADCs”. Elsevier Ltd on Procedia Technology (2016),No.25,574-581.
• 3. Gupta, Yogendra: Garg, Lokesh; Khandelwal, Sarthak; Gupta, Sanchit; Saini, Sandeep,Design of low power and high-speed multiplexer-based Thermometer to Gray encoder”, [IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) - Naha-shi, Japan,(2013), 501–504.
• 4. Sarang. S, Karale, Dhanashri, M. Hogale,Design of 876 MSPS, 2.5v, 250nm, 4-Bit Flash ADC using Quantum Voltage Comparator and Pseudo Logic Encoder”. International Journal of Engineering Research & Technology [IJERT],2019,974-978.
• 5. Arunkumar. P, Chavan, Rekha. G, P. Narashimaraja. Design of a 1.5-V, 4-bit Flash ADC using 90nm Technology”. International Journal of Engineering and Advanced Technology [IJEAT] ISSN:2249 – 8958.
• 6. Proesel, Jonathan E.; Pileggi, Lawrence T.,A 0.6-to-1V inverter-based 5-bit flash ADC in 90nm digital CMOS”, IEEE Custom Integrated Circuits Conference - CICC 2008 - San Jose, CA, USA ,IEEE Custom Integrated Circuits Conference, (2008),153–156.
• 7. Nirali Hemant Patel.,Power Efficient 4-bit Flash ADC using Cadence Virtuoso”. International Journal of Engineering Research & Technology [IJERT],(2021) 2278-0181
• 8. Jiangpeng Wanga, Wing-ShanTam, Chi-Wah Kok & Kong-Pang Puna,A 5-bit 500MS/s flash ADC with temperature-compensated inverter-based comparator". Solid-State Electronics Letters,(2020),2589-2088.
• 9. Nasrollahpour, Mehdi; Hamedi-Hagh, Sotoudeh,Extra Bit Generation for High-Speed Time-Based Flash ADCs in 65nm CMOS.”. [IEEE International Symposium on Circuits and Systems (ISCAS) - Florence, Italy (2018),1-5.
• 10. Shylu, D.S., Radha, Paul, P. Sam, Sudeepa, Parakati Sarah (2019). “Design of low power 4-bit Flash ADC in 90nm CMOS Process”, [IEEE 2019 2nd International Conference on Signal Processing and Communication (ICSPC) - Coimbatore, India (201),252–257.
• 11. Roohollah Sanati, Farzan Khatib ,Mohammad Javadian Sarraf, Reihaneh Kardehi Moghaddam (2021) “ Low power Bulk-Driven Time-Domain Comparator with High Voltage-to-Time Gain” Tabriz Journal of Electrical Engineering (TJEE), vol. 51, ( 2021), No. 4,98-106.
• 12. Aneesh, K., G. Manoj, and D.S. Shylu Sam. "Design Approaches of Ultra-Low Power SAR ADC for Biomedical Systems—A Review." Journal of Circuits, Systems and Computers,vol 31,No:12,(2022),1-32.
• 13. Ata Khorami, Roghayeh Saeidi, Manoj Sachdev , Mohammad Sharifkhani,A low power dynamic comparator for low offset - applications”, Integration- The VLSI Journal,Vol.69,(2019),23- 30.
• 14. D.S.Shylu, P.Sam Paul ,A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique, Circuit World,47(3),(2021),274-283.
• 15. Avaneesh K. Dubey, R.K. Nagaria (2018) “Optimization for offset and kickback- noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load", Analog Integrated Circuits and Signal Processing,vol.10,(2),(2019),307-317.
• 16. D.S.Shylu ,D.Jackuline Moni,P.Sam Paul, D.Nirmal,A Novel architecture of 10-bit 40MSPS low power pipelined ADC using a simultaneous Capacitor and Op-amp sharing Technique, Silicon, Springer, (2021),No.14,4839-4847.
• 17. Shylu D.S.,Jackuline Moni D.,“A 1.8V 22mW 10 bit 165 MSPS Pipelined ADC for Video Applications”, WSEAS Transactions on Circuits and systems,vol. 13, (2014),343-355.
• 18. D.S. Shylu Sam, S. Radha, D. Jackuline Moni, P. Sam Paul, J. Jecintha, “Design of 1-V, 12-Bit Low Power Incremental Delta Sigma ADC for CMOS Image Sensor Applications”, International Journal of Recent Technology and Engineering (IJRTE),(2019) vol.7, no. 5S3, 249-254.
• 19. Shylu David Sundararaj, D. Jackuline Moni, and G. Nivetha. "Design and power optimization of high-speed pipelined ADC with programmable gain amplifier for wireless receiver applications.Wireless Personal Communications, 90,(2016),657-678.
• 20. D. S. Shylu Sam, P. Sam Paul, Diana Jeba Jingle, P. Mano Paul, Judith Samuel, J. Reshma, P. Sarah Sudeepa, G. Evangeline."Design of Low–power 4-bit Flash ADC Using Multiplexer Based Encoder in 90nm CMOS Process."Intl Journal of Electronics And Telecommunications,Vol. 68, No. 3, (2022),565-570.D. S. Shylu , P. Sam Paul , D. Jackuline Moni , J. Arolin Monica Helan " A power efficient delta-sigma ADC with series-bilinear switch capacitor voltage-controlled oscillator, TELKOMNIKA Telecommunication, Computing, Electronics and Control, Vol. 18, No. 5, (2020), pp. 2618-2627.