A low-power 100MS/s Flash ADC with thermometer code encoding technique for automotive applications

• Autorzy: Golda Persiya Gnana , Sam D.S.Shylu , Paul Sam P. , Jayanthi D.

Identyfikatory

DOI

10.15199/48.2024.10.15

Warianty tytułu

PL

Przetwornik ADC Flash o niskim poborze mocy 100 MS/s z techniką kodowania kodu termometru do zastosowań motoryzacyjnych

• Języki publikacji: EN

Abstrakty

EN

A 3-bit 100MS/s flash Analog-to-Digital Converter (ADC) with thermometer code encoding technique is proposed. A novel XOR-based thermometer to a gray encoder and clocked PMOS-based dynamic comparator is designed. Flash ADC design compares the input voltage to a predetermined reference value using comparators to produce a gray code output. To improve the power efficiency PMOS based dynamic comparator is used. Conventional Dynamic latched comparators suffer from kickback noise, which lowers the performance of Flash ADC. To overcome this problem, a new architecture of dynamic latched comparator with PMOS technique is designed. The proposed Flash ADC uses the conversion of thermometer to gray coding to reduce the bubble errors. Based on the simulation results the proposed Flash ADC consumes 2.4mW of power when operating at 100 MHz and a 1.8 V power supply. The proposed flash ADC achieves excellent accuracy and low power consumption by utilizing a novel thermometer code encoding technique.

PL

Zaproponowano 3-bitowy 100MS/s flash Analog-to-Digital Converter (ADC) z techniką kodowania kodu termometru. Zaprojektowano nowy termometr oparty na XOR do enkodera Graya i taktowanego komparatora dynamicznego opartego na PMOS. Projekt Flash ADC porównuje napięcie wejściowe do ustalonej wartości odniesienia za pomocą komparatorów w celu wygenerowania wyjścia kodu Graya. Aby poprawić wydajność energetyczną, zastosowano komparator dynamiczny oparty na PMOS. Konwencjonalne komparatory dynamiczne z zatrzaskiem są narażone na szum odrzutu, który obniża wydajność Flash ADC. Aby przezwyciężyć ten problem, zaprojektowano nową architekturę komparatora dynamicznego z zatrzaskiem z techniką PMOS. Proponowany Flash ADC wykorzystuje konwersję termometru na kodowanie Graya w celu zmniejszenia błędów pęcherzyków. Na podstawie wyników symulacji proponowany Flash ADC zużywa 2,4 mW mocy podczas pracy przy 100 MHz i zasilaniu 1,8 V. Proponowany flash ADC osiąga doskonałą dokładność i niskie zużycie energii dzięki wykorzystaniu nowatorskiej techniki kodowania kodu termometru.

Słowa kluczowe

EN

clocked PMOS technique; dynamic latch comparator; flash analog-to-digital converter; thermometer code encoding technique

PL

technika zegarowego PMOS; komparator dynamicznego zatrzasku; przetwornik analogowo-cyfrowy Flash; technika kodowania kodu termometru

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2024
• Tom: R. 100, nr 10
• Strony: 84--88
• Opis fizyczny: Bibliogr. 38 poz., rys., tab.

Twórcy

autor

Golda Persiya Gnana

• Department of Electronics & Communication Engineering, Karunya Institute of Technology and Sciences, Coimbatore, 641114

autor

Sam D.S.Shylu

• Department of Electronics & Communication Engineering, Karunya Institute of Technology and Sciences, Coimbatore, 641114

autor

Paul Sam P.

• Department of Mechanical Engineering Karunya Institute of Technology and Sciences, Coimbatore, India

autor

Jayanthi D.

• Department of Electronics & Communication Engineering Rajalakshmi Engineering College, Chennai

Bibliografia

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• 2. Esmailiyan, A., Schembari, F. and Staszewski, R.B., A 0.36-V 5 MS/s time-mode flash ADC with Dickson-charge-pump-based comparators in 28-nm CMOS. IEEE Transactions on Circuits and Systems I: Regular Papers, 67(6), pp.1789-1802(2020).
• 3. Yi, I.M., Miura, N., Fukuyama, H. and Nosaka, H., A 15.1-mW 6 GS/s 6-bit single-channel flash ADC with selectively activated 8× time-domain latch interpolation. IEEE Journal of Solid-State Circuits, 56(2), pp.455-464(2020).
• 4. Zhu, S., Wu, B., Cai, Y. and Chiu, Y., A 2-GS/s 8-bit non interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 53(4), pp.1172-1183(2017).
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• 12. Zhu, S., Wu, B., Cai, Y. and Chiu, Y., A 2-GS/s 8-bit non interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 53(4), pp.1172-1183(2017).
• 13. Kim, J.I., Oh, D.R., Jo, D.S. and Ryu, S.T., A 65 nm CMOS 7b 2 GS/s 20.7 mW flash ADC with cascaded latch interpolation. IEEE Journal of Solid-State Circuits, 50(10), pp.2319-2330(2015).
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• 20. Fan, Q. and Chen, J., A 1-GS/s 8-bit 12.01-fJ/conv.-step two-step SAR ADC in 28-nm FDSOI technology. IEEE Solid-State Circuits Letters, 2(9), pp.99-102(2019).
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• 25. Kim, J.I., Oh, D.R., Jo, D.S. and Ryu, S.T., A 65 nm CMOS 7b 2 GS/s 20.7 mW flash ADC with cascaded latch interpolation. IEEE Journal of Solid-State Circuits, 50(10), pp.2319-2330(2015).
• 26. Oh, D.R., Kim, J.I., Jo, D.S., Kim, W.C., Chang, D.J. and Ryu, S.T., A 65-nm CMOS 6-bit 2.5-GS/s 7.5-mW 8$\times $ time-domain interpolating flash ADC with sequential slope-matching offset calibration. IEEE Journal of Solid-State Circuits, 54(1), pp.288 297(2018).
• 27. Tretter, G., Khafaji, M.M., Fritsche, D., Carta, C. and Ellinger, F., Design and characterization of a 3-bit 24-GS/s flash ADC in 28-nm low-power digital CMOS. IEEE Transactions on Microwave Theory and Techniques, 64(4), pp.1143-1152(2016).
• 28. Zhu, S., Wu, B., Cai, Y. and Chiu, Y., A 2-GS/s 8-bit non interleaved time-domain flash ADC based on remainder number system in 65-nm CMOS. IEEE Journal of Solid-State Circuits, 53(4), pp.1172-1183(2017).
• 29. Yi, I.M., Miura, N., Fukuyama, H. and Nosaka, H., A 15.1-mW 6 GS/s 6-bit single-channel flash ADC with selectively activated 8× time-domain latch interpolation. IEEE Journal of Solid-State Circuits, 56(2), pp.455-464(2020).
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• 32. Sam, D.S. and Paul, P.S., A 10-bit 200 MS/s pipelined ADC with parallel sampling and switched op-amp sharing technique. Circuit World, 47(3), pp.274-283(2021).
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• 37. Shylu Sam, D.S., Sam Paul, P., Enoch Mani Deepak, B., Shirley Eva Paul, B., Jayanth, B., Pavitra Kumar, K. Design and Comparison of Low Power Consumption Binary and Quaternary Multipliers, National Academy Science Letters. (2023).Article in Press.
• 38.Aneesh, K., Manoj, G., Shylu Sam, S. Design Approaches of Ultra Low Power SAR ADC for Biomedical Systems - A Review (2022) Journal of Circuits, Systems and Computers, 31 (12).

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki i promocja sportu (2025).