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Abstrakty
Electronic circuit boards are components widely used in applications requiring modern high-speed signal transmission. This study aims to comprehensively examine various methods used in the design and manufacturing stages of electronic circuit boards and to focus on strategies for reducing crosstalk. In addition, the effects of these methods are thoroughly analyzed by comparing simulation results and laboratory tests found in the literature. Effectively managing crosstalk can aid in preserving signal integrity in circuits characterized by high speed and density.
Rocznik
Tom
Strony
113--121
Opis fizyczny
Bibliogr. 30 poz., tab., rys.
Twórcy
autor
- Dogus University, Turkiye
autor
- Dogus University, Turkiye
autor
- Dogus University, Turkiye
Bibliografia
- [1] M. Shoji, Theory of CMOS Digital Circuits and Circuit Failures, Princeton, NJ: Princeton University Press, 1992.
- [2] C. Smartt, D.W.P. Thomas, H. Nasser, M.H. Baharuddin, G. Gradoni, S.C. Creagh, et al., "Challenges of time domain measurement of field-field correlation for complex PCBs," 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC), Dresden, Germany, 2015, pp. 953-958, doi: 10.1109/ISEMC.2015.7256294
- [3] Y. Kuznetsov et al., "Cyclostationary Characterization of the Interference Induced by Crosstalk Between Transmission Lines," 2019 International Symposium on Electromagnetic Compatibility EMC EUROPE, Barcelona, Spain, 2019, pp. 574-579, doi:10.1109/EMCEurope.2019.8871986
- [4] D. Brooks, PCB Currents How They Flow How They React, Prentice Hall, 2013
- [5] I. Novak, B. Eged and L. Hatvani, "Measurement by vector-network analyzer and simulation of crosstalk reduction on printed circuit boards with additional center traces," 1993 IEEE Instrumentation and Measurement Technology Conference, Irvine, CA, USA, 1993, pp. 269-274, doi: 10.1109/IMTC.1993.382637
- [6] J.V.R. Ravindra and M.B. Srinivas, "Modeling and Analysis of Crosstalk for Distributed RLC Interconnects using Difference Model Approach", Rio de Janeiro Brazil SBCCI '07, September 3–6, 2007
- [7] C. -Y. Hsiao, C. -H. Huang, C. -D. Wang, K. -H. Liao, C. -H Shen, C. -C. Wang and T. -L. Wu, "Mold-based compartment shielding to mitigate the intra-system coupled noise on SiP modules," 2011 IEEE International Symposium on Electromagnetic Compatibility, Long Beach, CA, USA, 2011, pp. 341-344, doi: 10.1109/ISEMC.2011.6038333
- [8] A. Seyedolhosseini, N. Masoumi and M. Mehri, "A rigorous analytical method for waveform extraction of fully coupled RLC nano-scale interconnects to PCB traces," 2012 Second Conference on Millimeter-Wave and Terahertz Technologies (MMWaTT), Tehran, Iran, 2012, pp. 40-43, doi: 10.1109/MMWaTT.2012.6532163
- [9] L. Zhi, W. Qiang and S. Changsheng, "Application of guard traces with vias in the RF PCB layout," 2002 3rd International Symposium on Electromagnetic Compatibility, Beijing, China, 2002, pp. 771-774, doi:10.1109/ELMAGC.2002.1177544
- [10] K. Sehat and N. Masoumi, "Crosstalk noise analysis for unequal length interconnects on PCBs using length dependent parameters," 2015 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), Istanbul, Turkey, 2015, pp. 1-4, doi: 10.1109/SMACD.2015.7301692
- [11] A. A. Bajwa, S. Jangam, S. Pal, N. Marathe, T. Bai, T. Fukushima, M. Goorsky and S. S. Iyer, "Heterogeneous Integration at Fine Pitch (≤ 10 μm) Using Thermal Compression Bonding," 2017 IEEE 67th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2017, pp. 1276-1284, doi: 10.1109/ECTC.2017.240
- [12] T. Shibata and A. Takahashi, "Flexible opto-electronic circuit board for in-device interconnection", 2008 58th Electronic Components and Technology Conference Lake Buena Vista, pp. 261-267, 2008, doi: 10.1109/ECTC.2008.4549980
- [13] J. Zhang and E. G. Friedman, "Crosstalk noise model for shielded interconnects in VLSI-based circuits," IEEE International [Systems-on-Chip] SOC Conference, 2003. Proceedings., Portland, OR, USA, 2003, pp. 243-244, doi: 10.1109/SOC.2003.1241502
- [14] U. Choi, Y. -J. Kim and Y. -S. Kim, "Crosstalk reduction in printed circuit boards using irregularly-spaced vias in a guard trace over a slotted ground plane," 2009 European Conference on Circuit Theory and Design, Antalya, Turkey, 2009, pp. 794-797, doi: 10.1109/ECCTD.2009.5275103
- [15] W. T. Huang, C. H. Lu, ve D. B. Lin, "Design of suppressing crosstalk by vias of serpentine guard trace," PIERS Online, cilt 6, no. 4, ss. 360-364, 2010, doi: 10.2529/PIERS090906235243
- [16] F. D. Mbairi, W. P. Siebert and H. Hesselbom, "On The Problem of Using Guard Traces for High Frequency Differential Lines Crosstalk Reduction," in IEEE Transactions on Components and Packaging Technologies, vol. 30, no. 1, pp. 67-74, March 2007, doi: 10.1109/TCAPT.2007.892072
- [17] X. -B. Yu, Q. -M. Cai, Y. Ren, X. Ye and J. Fan, "Study of Thickening Soldermask Coated Microstrip Lines on High-Speed PCBs for Crosstalk Reduction in DDR5," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 575-577, doi: 10.1109/EMCSI38923.2020.9191539
- [18] Q. -M. Cai, Y. Zhu, R. Zhang, Y. Ren, X. Ye and J. Fan, "A Study of Coverlay Coated Microstrip Lines for Crosstalk Reduction in DDR5," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 581-585, doi: 10.1109/EMCSI38923.2020.9191683
- [19] A. Suntives, A. Khajooeizadeh and R. Abhari, "Using via fences for crosstalk reduction in PCB circuits," 2006 IEEE International Symposium on Electromagnetic Compatibility, 2006. EMC 2006., Portland, OR, USA, 2006, pp. 34-37, doi: 10.1109/ISEMC.2006.1706258
- [20] M. Almalkawi, K. Shamaileh, S. Abushamleh, Y. Choukiker and V. Devabhaktuni, "Effect of PCB traces with continuous impedance perturbation on crosstalk immunity," IEEE MTT-S International Microwave and RF Conference, New Delhi, India, 2013, pp. 1-4, doi: 10.1109/IMaRC.2013.6777699
- [21] M. S. Sharawi, "Practical issues in high speed PCB design," in IEEE Potentials, vol. 23, no. 2, pp. 24-27, April-May 2004, doi: 10.1109/MP.2004.1289994
- [22] D. -B. Lin, C. -P. Huang, C. -H. Lin, H. -N. Ke and W. -S. Liu, "Using rectangular-patches (RPs) to reduce far-end crosstalk noise and improve eye-diagrams on microstrip helix delay line," 2015 IEEE International Symposium on Electromagnetic Compatibility (EMC), Dresden, Germany, 2015, pp. 612-615, doi: 10.1109/ISEMC.2015.7256233
- [23] Q. -M. Cai, X. -B. Yu, L. Zhang, L. Zhu, C. Zhang, Y. Ren and J. Fan, "Far-End Crosstalk Mitigation in DDR5 Using Graphene-Paraffin Material Coated Signal Lines with Tabs," 2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), Taiyuan, China, 2019, pp. 1-3, doi: 10.1109/CSQRWC.2019.8799170
- [24] D. D. Zhang, D. L. Zhao, J. M. Zhang et al., "Microwave absorbing property and complex permittivity and permeability of graphene–CdS nanocomposite", Journal of Alloys and Compounds, vol. 589, pp. 378-383, 2014, doi: 10.1016/j.jallcom.2013.11.195
- [25] L. Zhang, Q. M. Cai, X. B. Yu, L. Zhu, C. Zhang, Y. Ren, and J. Fan, "Far-End Crosstalk Mitigation for Microstrip Lines in High-Speed PCBs," 2019 Cross Strait Quad-Regional Radio Science and Wireless Technology Conference (CSQRWC), Taiyuan, China, 2019, pp. 1-3, doi: 10.1109/CSQRWC.2019.8799209
- [26] I. -Y. Park, I. Ahmed, D. Brunker, P. Xie and J. Natarajan, "Effects of Various Via Patterns on Resonance and Crosstalk in High Speed Printed Circuit Boards," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 164-169, doi: 10.1109/EMCSI38923.2020.9191554
- [27] Y. Shim and D. Oh, "Improved PCB via pattern to reduce crosstalk at package BGA region for high speed serial interface," 2014 IEEE 64th Electronic Components and Technology Conference (ECTC), Orlando, FL, USA, 2014, pp. 1896-1901, doi: 10.1109/ECTC.2014.6897560
- [28] J. H. Lee, "A novel meander split power/ground plane reducing crosstalk of traces crossing over," Electronics, cilt 8, no. 9, s. 1041, 2019, doi: 10.3390/electronics8091041
- [29] F. Xiao, Y. Nakada, K. Murano, ve Y. Kami, "Crosstalk analysis model for traces crossing split ground plane and its reduction by stitching capacitor," Electronics and Communications in Japan (Part II: Electronics), cilt 90, no. 1, ss. 26-34, 2007. doi: 10.1002/ecjb.20338
- [30] J. Wang, C. Xu, S. Zhong, S. Bai, J. Lee and D. Kim, "Differential Via Designs for Crosstalk Reduction in High-Speed PCBs," 2020 IEEE International Symposium on Electromagnetic Compatibility & Signal/Power Integrity (EMCSI), Reno, NV, USA, 2020, pp. 145-149, doi: 10.1109/EMCSI38923.2020.9191558
Uwagi
Opracowanie rekordu ze środków MNiSW, umowa nr POPUL/SP/0154/2024/02 w ramach programu "Społeczna odpowiedzialność nauki II" - moduł: Popularyzacja nauki (2025).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-d0eba2a3-3925-4862-be40-eb4f6368a63c
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