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Design Exploration of AES Accelerators on FPGAs and GPUs

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The embedded systems are increasingly becoming a key technological component of all kinds of complex technical systems and an exhaustive analysis of the state of the art of all current performance with respect to architectures, design methodologies, test and applications could be very interesting. The Advanced Encryption Standard (AES), based on the well-known algorithm Rijndael, is designed to be easily implemented in hardware and software platforms. General purpose computing on graphics processing unit (GPGPU) is an alternative to recongurable accelerators based on FPGA devices. This paper presents a direct comparison between FPGA and GPU used as accelerators for the AES cipher. The results achieved on both platforms and their analysis has been compared to several others in order to establish which device is best at playing the role of hardware accelerator by each solution showing interesting considerations in terms of throughput, speedup factor, and resource usage. This analysis suggests that, while hardware design on FPGA remains the natural choice for consumer-product design, GPUs are nowadays the preferable choice for PC based accelerators, especially when the processing routines are highly parallelizable.
Słowa kluczowe
Rocznik
Tom
Strony
28--38
Opis fizyczny
Bibliogr. 32 poz., rys., tab.
Twórcy
autor
  • Faculty of Engineering and Architecture University of Enna KORE Via delle Olimpiadi - Cittadella Universitaria 94100 Enna, Italy
autor
  • Department of Biopathology and Medical Biotechnologies University of Palermo Via del Vespro 129 90127 Palermo, Italy
Bibliografia
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  • [3] K. F. K. Wong, V. Yap, and T. P. Chiong, “Hardware accelerator implementation on FPGA for video processing”, in Proc. IEEE Conf. on Open Syst. ICOS 2013, Kuching, Malaysia, 2013, pp. 47–51 (doi: 101109/ICOS.2013.6735046).
  • [4] V. Conti, C. Militello, F. Sorbello, and S. Vitabile, “Biometric sensors rapid prototyping on FPGA”, The Knowl. Engin. Rev., vol. 30, no. 2, pp. 201–219, 2015.
  • [5] C. Militello, V. Conti, S. Vitabile, and F. Sorbello, “An embedded iris recognizer for portable and mobile devices”, Comp. Syst. Science and Engin., vol. 25, no. 2, pp. 119–131, 2010.
  • [6] N. Neveset et al., “BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment”, in Proc. Int. IEEE Conf. on Appli.-Spec. Syst., Architec. & Process. ASAP 2013, Ashburn, VA, USA, 2013, pp. 241–244.
  • [7] E. Fusella, A. Cilardo, and A. Mazzeo, “Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip”, in Proc. 25th Int. IEEE Conf. on Field Programmable Logic & Appl. FPL 2015, London, UK, 2015, pp. 1–2.
  • [8] S. Vitabile, V. Conti, C. Militello, and F. Sorbello, “An extended jade-s based framework for developing secure multi-agent systems”, Comp. Stand. and Interfaces, vol. 31, no. 5, pp. 913–930, 2009.
  • [9] Y. Wang and Y. Ha, “FPGA based Rekeying for cryptographic key management in Storage Area Network”, in Proc. 23rd Int. IEEE Conf. on Field Programmable Logic and Appl. FPL 2013, Porto, Portugal, 2013, pp. 1–6.
  • [10] C. Militello, V. Conti, S. Vitabile, and F. Sorbello, “Embedded access points for trusted data and resources access in HPC systems”, The J. of Supercomput., vol. 55, no. 1, pp. 4–27, 2011.
  • [11] B. Cope, P. Cheung, W. Luk, and S. Witt, “Have GPUs made FPGAs redundant in the field of video processing?”, in Proc. Int. IEEE Conf. on Field-Programmable Technol. FPT 2005, Singapore, 2005, pp. 111–118.
  • [12] A. B. M. Mali and F. Novak, “Hardware implementation of AES algorithm”, J. of Elec. Engin., vol. 56, no. 9–10, pp. 265–269, 2005.
  • [13] Z. Baker, M. Gokhale, and J. Tripp, “Matched filter computation on FPGA, cell and GPU”, in Proc. 15th IEEE Symp. on FieldProgrammable Custom Comput. Machin. FCCM 2007, Napa, CA, USA, 2007, pp. 207–218.
  • [14] S. Che, J. Li, J. Sheaffer, K. Skadron, and J. Lach, “Accelerating compute-intensive applications with GPUs and FPGAs”, in Proc. Symp. on Appl. Specific Process. SASP 2008, Anaheim, CA, USA, 2008, pp. 101–107.
  • [15] S. Asano, T. Maruyama, and Y. Yamaguchi, “Performance comparison of FPGA, GPU and CPU in image processing”, in Proc. 19th Int. IEEE Conf. on Field Programmable Logic and Appl. FPL 2009, Prague, Czech Republic, 2009, pp. 126–131.
  • [16] N. Kapre and A. DeHon, “Performance comparison of singleprecision spice model-evaluation on FPGA, GPU, cell, and multicore processors”, in Proc. 19th Int. IEEE Conf. on Field Programmable Logic and Appl. FPL 2009, Prague, Czech Republic, 2009, pp. 65–72.
  • [17] Y. Zhang, Y. Shalabi, R. Jain, K. Nagar, and J. Bakos, “FPGA vs. GPU for sparse matrix vector multiply”, Proc. Int. IEEE Conf. on Field-Programmable Technol. FPT 2009, Sydney, Australia, 2009, pp. 255–262.
  • [18] K. Theoharoulis, C. Antoniadis, N. Bellas, and C. Antonopoulos, “Implementation and performance analysis of seal encryption on FPGA, GPU and multi-core processors”, in Proc. 19th Ann. Int. IEEE Symp. on Field-Programmable Custom Comput. Machines FCCM 2011, Salt Lake City, UT, USA, 2011, pp. 65–68.
  • [19] “Federal Information Processing Standards Publication 197”, Tech. rep., National Institute of Standards and Technology, 2001 [Online]. Available: http://csrc.nist.gov/publications/fips/fips197/fips-197.pdf
  • [20] M. Dworkin, “Recommendation for Block Cipher Modes of Operation”, Tech. rep., National Institute of Standards and Technology, 2001 [Online]. Available: http://csrc.nist.gov/publications/ nistpubs/800-38a/sp800-38a.pdf
  • [21] Celoxica – Mentor Graphics, Handel-C advanced optimization [Online]. Available: https://www.mentor.com/
  • [22] Celoxica – Mentor Graphics, RC1000 Hardware Reference Manual [Online]. Available: https://www.mentor.com/
  • [23] Cypress. CY7C1049 512K x 8 Static RAM datasheet [Online]. Available: http://www.cypress.com/file/42811/download
  • [24] “The OpenCL Specification v 1.2”, Tech. rep., Khronos OpenCL Working Group, 2011 [Online]. Available: http://www.khronos.org/ registry/cl/specs/opencl-1.2.pdf
  • [25] T. Hoang and V. L. Nguyen, “An efficient FPGA implementation of the advanced encryption standard algorithm”, in Proc. Int. IEEE Conf. on Comput. & Commun. Technol., Res., Innov., and Vision for the Future RIVF 2012, Ho Chi Minh, Vietnam, 2012, pp. 1–4.
  • [26] N. S. E. Rodriguez-Henriquez and A. Diaz-Pkrez, “4.2 Gbit/s singlechip FPGA implementation of AES algorithm”, Electron. Lett., vol. 39, no. 15, pp. 1115–1116, 2003.
  • [27] D. Kotturi, S.-M. Yoo, and J. Blizzard, “AES crypto chip utilizing high-speed parallel pipelined architecture”, in Proc. Int. IEEE Symp. on Circ. and Syst. ISCAS 2005, Kobe, Japan, 2005, vol. 5, pp. 4653–4656.
  • [28] C. Sivakumar and A. Velmurugan, “High speed VLSI design CCMP AES cipher for WLAN (IEEE 802.11i)”, Int. Conf. on Sig. Process., Commun., Chennai, India, 2007, pp. 398–403.
  • [29] R. M. Gurmail Singh, “FPGA based high speed and area efficient AES encryption for data security”, Int. J. of Res. and Innov. in Comp. Engin., vol. 1, no. 2, pp. 53–56, 2011.
  • [30] S. Manavski, “CUDA compatible GPU as an efficient hardware accelerator for AES cryptography”, in Proc. International IEEE Conference on Signal Processing and Communications ICSPC 2007, Dubai, United Arab Emirates, 2007, pp. 65–68.
  • [31] X. Wang, X. Li, M. Zou, and J. Zhou, “AES finalists implementation for GPU and multi-core CPU based on OpenCL”, in Proc. Int. IEEE Conf. on Anti-Counterfeiting, Secur. & Identif. ASID 2011, Xiamen, China, 2011, pp. 38–42.
  • [32] T. K. Keisuke Iwai, N. Nishikawa, “Acceleration of AES encryption on CUDA GPU”, Int. J. of Netw. & Comput., vol. 2, no. 1, pp. 131–145, 2011.
Uwagi
Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę (zadania 2017).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-d0dd07c3-7a49-4ef8-a826-7fbe29f0d4d6
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