Identyfikatory
Warianty tytułu
Języki publikacji
Abstrakty
A low drop-out [LDO] voltage regulator with fast transient response which does not require capacitor for proper operation is proposed in this paper. Recent cap-less LDOs do not use off chip capacitor but instead they use on chip capacitor which occupy large area on chip. In the proposed LDO this on chip capacitor is also avoided. A novel secondary local feed-back technique is introduced which helps to achieve a good transient response even in the absence of output capacitor. Further a self compensating error amplifier is selected to eliminate the need of compensating capacitor. Stability analysis shows that the proposed LDO is stable with a phase margin of 78 0. The proposed LDO is laid out using Cadence spectre in 180 nm standard CMOS technology. Post layout simulation is carried out and LDO gives 6mV/V and 360μV /mA line and load regulation respectively. An undershoot of 120 mV is observed during the load transition from 0 mA to 50 mA with 1 μs transition time, however LDO is able to recover within 1.4μs. Since capacitor is not required in any part of design, it occupies only 0.010824 mmXmm area on chip.
Słowa kluczowe
Rocznik
Tom
Strony
159--165
Opis fizyczny
Bibliogr. 20 poz., rys., wykr., tab.
Twórcy
autor
- Faculty of Electronics and Communication, Manipal Institute of Technology, MAHE deemed to be University, Manipal, India
autor
- Faculty of Electronics and Communication, Manipal Institute of Technology, MAHE deemed to be University, Manipal, India
Bibliografia
- [1] Y. Zeng, Y. Li, X. Zhang, and H.-z. Tan, “A push-pulled fvf based outputcapacitorless ldo with adaptive power transistors,” Microelectronics Journal, vol. 64, pp. 69–77, 2017.
- [2] A. Saberkari, E. Alarcon, and S. B. Shokouhi, “Fast transient currentsteering cmos ldo regulator based on current feedback amplifier,” Integration, the VLSI Journal, vol. 46, no. 2, pp. 165–171, 2013.
- [3] J. Hinojo, C. Lujan-Martinez, A. Torralba, and J. Ramirez-Angulo, “Internally compensated ldo regulator based on the cascoded fvf,” Microelectronics Journal, vol. 45, no. 10, pp. 1268–1274, 2014.
- [4] S.-K. Kao, Y.-Z. Lee, C.-Y. Ku, and H.-C. Cheng, “Output capacitorfree low-dropout regulator with fast transient response and ultra small compensation capacitor,” Microelectronics Journal, vol. 56, pp. 134–141, 2016.
- [5] X. Ming, N. Li, X.-m. Zhang, Y. Lu, Z.-k. Zhou, and Z. Wang, “Acapacitor-less ldo regulator with dynamic transconductance enhancement technique,” Analog Integrated Circuits and Signal Processing, vol. 84, no. 3, pp. 433–444, 2015.
- [6] J. Yeo, K. Javed, J. Lee, J. Roh, and J.-D. Park, “A capacitorless lowdropout regulator with enhanced slew rate and 4.5ua quiescent current,” Analog Integrated Circuits and Signal Processing, vol. 90, no. 1, pp. 227–235, 2017.
- [7] Y. Yosef-Hay, D. O. Larsen, P. L. Muntal, and I. H. Jorgensen, “Fully integrated, low drop-out linear voltage regulator in 180 nm cmos,” Analog Integrated Circuits and Signal Processing, pp. 1–10, 2017.
- [8] C.-M. Chen, T.-W. Tsai, and C.-C. Hung, “Fast transient low-dropout voltage regulator with hybrid dynamic biasing technique for soc application,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 21, no. 9, pp. 1742–1747, 2013.
- [9] J. Esteves, J. Pereira, J. Paisana, and M. Santos, “Ultra low power capless ldo with dynamic biasing of derivative feedback,” Microelectronics Journal, vol. 44, no. 2, pp. 94–102, 2013.
- [10] Y.-i. Kim and S.-s. Lee, “A capacitorless ldo regulator with fast feedback technique and low-quiescent current error amplifier,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 60, no. 6, pp. 326–330, 2013.
- [11] C. Li and P. K. Chan, “Fvf ldo regulator with dual dynamic-load composite gain stage,” Analog Integrated Circuits and Signal Processing, pp. 1–10, 2017.
- [12] S. J. Yun, J. S. Kim, and Y. S. Kim, “Capless ldo regulator achieving-76 db psr and 96.3 fs fom,” IEEE Transactions on Circuits and Systems II: Express Briefs, 2016.
- [13] X. Han, T. Burger, and Q. Huang, “An output-capacitor-free adaptively biased ldo regulator with robust frequency compensation in 0.13 m cmos for soc application,” in Circuits and Systems (ISCAS), 2016 IEEE International Symposium on. IEEE, 2016, pp. 2699–2702.
- [14] K. N. Leung and P. K. Mok, “A capacitor-free cmos low-dropout regulator with damping-factor-control frequency compensation,” IEEE Journal of Solid-State Circuits, vol. 38, no. 10, pp. 1691–1702, 2003.
- [15] S. K. Lau, P. K. Mok, and K. N. Leung, “A low-dropout regulator for soc with q-reduction,” IEEE Journal of Solid-State Circuits, vol. 42, no. 3, pp. 658–664, 2007.
- [16] X. L. Tan, S. S. Chong, P. K. Chan, and U. Dasgupta, “A ldo regulator with weighted current feedback technique for 0.47 nf–10 nf capacitive load,” IEEE Journal of Solid-State Circuits, vol. 49, no. 11, pp. 2658–2672, 2014.
- [17] H. Banba, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, and K. Sakui, “A cmos bandgap reference circuit with sub-1-v operation,” IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 670–674, 1999.
- [18] S. Hongprasit, W. Sa-Ngiamvibool, and A. Aurasopon, “Design of bandgap core and startup circuits for all cmos bandgap voltage reference,” PRZEGLAD ELEKTROTECHNICZNY, vol. 88, no. 4 A, pp. 277–280, 2012.
- [19] C. J. B. Fayomi, G. I. Wirth, H. F. Achigui, and A. Matsuzawa, “Sub 1 v cmos bandgap reference design techniques: a survey,” Analog Integrated Circuits and Signal Processing, vol. 62, no. 2, pp. 141–157, 2010.
- [20] P. Perez-Nicoli, F. Veirano, P. C. Lisboa, and F. Silveira, “Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror,” Analog Integrated Circuits and Signal Processing, vol. 89, no. 3, pp. 521–529, 2016.
Uwagi
Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2019).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-c8b9c88d-00ce-4c2f-a7ab-14466ed2db0c