On the systematic method of conditional control program execution by a PLC

• Autorzy: Milik A. , Chmiel M. , Hrynkiewicz E.

Identyfikatory

DOI

10.1515/bpasts-2016-0018

• Języki publikacji: EN

Abstrakty

EN

The paper presents an original idea of the selective control program execution that allows significant response time reduction. The exhaustive analysis of the PLC program performance is given. An analytic approach explains the idea of the selective control program evaluation and gives the requirements for its feasibility. There is presented a systematic and formal method of program analysis based on a data flow graph approach. The method generates acyclic graph from the control program that is subject of optimization, variable allocation and instruction generation. The graph approach allows determining variables dependencies and task partitioning required by selective program execution. The method utilize the hardware supported variable changes detection. It is transparent for system operation and enables evaluation of blocks that require update.

Słowa kluczowe

EN

control program; PLC; LD; IL; FPGA; compiler; control program optimization; PLC programming; flow graph

PL

program sterujący; PLC; LD; IL; FPGA; kompilator; kontrola; optymalizacja oprogramowania; programowanie sterowników PLC; wykres przepływu

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2016
• Tom: Vol. 64, nr 1
• Strony: 161--170
• Opis fizyczny: Bibliogr. 21 poz., rys., tab., wykr.

Twórcy

autor

Milik A.

• Institute of Electronics, Silesian University of Technology of Gliwice, 16 Akademicka St., 44-100 Gliwice, Poland

autor

Chmiel M.

• Institute of Electronics, Silesian University of Technology of Gliwice, 16 Akademicka St., 44-100 Gliwice, Poland

autor

Hrynkiewicz E.

• Institute of Electronics, Silesian University of Technology of Gliwice, 16 Akademicka St., 44-100 Gliwice, Poland

Bibliografia

• [1] Cenelec, EN 61131-3, Programmable Controller - Part 3: Programming Languages, Int. Standard Management Centre, Brussels, 2013.
• [2] M. Chmiel and E. Hrynkiewicz, “Concurrent operation of processors in the bit-byte CPU of a PLC”, Control and Cybernetics 39 (2), 559-579 (2010).
• [3] M. Chmiel, “On reducing PLC response time”, Bull. Pol. Ac.: Tech. 56 (3), 229-238 (2008).
• [4] J. Klamka, “Controllability of dynamical systems. A survey”, Bull. Pol. Ac.: Tech. 61 (2), 335-342 (2013).
• [5] T. Klopot, P. Laszczyk, K. Stebel, and J. Czeczot, “Flexible function block implementation of the balance-based adaptive controller as the potential alternative for PID-based industrial applications”, Trans. Institute of Measurement and Control 36 (8), 1098-1113 (2014).
• [6] G. Valencia-Palomo and J.A. Rossiter, “Programmable logic controller implementation of an auto-tuned predictive control based on minimal plant information”, ISA Trans. 50, 92-100 (2011).
• [7] K.H. John and M. Tiegelkamp, IEC 61131-3: Programming Industrial Automation Systems: Concepts and Programming Languages, Requirements for Programming Systems, Decision- Making Aids, Springer-Verlag, Berlin, 2010.
• [8] K.H. Koo, G.S. Rho, and W.H. Kwon, “An architecture of the RISC processor for programmable controllers”, 20th Int. Conf. on Industrial Electronics, Control and Instrumentation IECON 94, 1179-1183 (1994).
• [9] S.A. Edwards, K. Sungjun, E.A. Lee, I. Liu, H.D. Patel, and M. Schoeberl, “A disruptive computer design idea: architectures with repeatable timing”, IEEE Int. Conf. on Computer Design 1, 54-59, (2009).
• [10] M. Chmiel, A. Malcher, and A. Nowara, “A metal sheet etching process control”, Machines, Technology, Materials 2, CDROM (1997), (in Polish).
• [11] A. Falcione and B.H. Krogh, “Design recovery for relay ladder logic”, IEEE Control Systems 13 (2), 90-98 (1993).
• [12] D. Du, X. Xiaodong, and Y. Kazuo, “A study on the generation of silicon-based hardware PLC by means of the direct conversion of the ladder diagram to circuit design language”, Int. J. Advanced Manufacturing Technology 49 (5), 615-626 (2010).
• [13] J. Mocha and D. Kania, “Hardware implementation of a control program in FPGA structures”, Przegląd Elektrotechniczny 88 (12a), 95-100 (2012).
• [14] A. Milik and E. Hrynkiewicz, “On translation of LD, IL and SFC given according to IEC-61131 for hardware synthesis of reconfigurable logic controller”, IFAC World Congress 19, 4477-4483 (2014).
• [15] Y. Yi and C. Haidan, “An optimizing compiler method to avoid partial invalid PLC instructions”, IEEE Int. Symp. on Industrial Electronics 1, 80-83 (2010).
• [16] A. Milik and A. Pulka, “On FPGA dedicated SFC synthesis and implementation according to IEC61131”, Int. Conf. on Signals and Electronic Systems 1, CD-ROM (2014).
• [17] N. Wirth, Algorithms + Data Structures = Programs, Prentice Hall, New York, 1976.
• [18] G. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publisher, Boston, 1996.
• [19] D. Gajski, N. Dutt, A. Wu, and S. Lin, High-Level Synthesis Introduction to Chip and System Design, Kluwer Academic Publishers, Boston, 1994.
• [20] H. Souleiman, S. O’Riain, and E. Curry, “Approximate semantic matching of heterogeneous events”, ACM Int. Conf. on Distributed Event-Based Systems 1, 252-263 (2012).
• [21] M. Chmiel, E. Hrynkiewicz, J. Mocha, and A. Milik, “Central processing units for PLC implementation in Virtex-4 FPGA”, IFAC World Congress 18, 6902-6907 (2011).

Uwagi

PL

Opracowanie ze środków MNiSW w ramach umowy 812/P-DUN/2016 na działalność upowszechniającą naukę.