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A fault verification method for testing of analogue electronic circuits

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
The paper deals with multiple soft fault diagnosis of analogue circuits. A method for diagnosis of linear circuits is developed, belonging to the class of the fault verification techniques. The method employs a measurement test performed in the frequency domain, leading to the nonlinear least squares problem. To solve this problem the Powell minimization method is applied. The diagnostic method is adapted to real circumstances, taking into account deviations of fault-free parameters and measurement uncertainty. Two examples of electronic circuits encountered in practice demonstrate that the method is efficient for diagnosis of middle-sized circuits. Although the method is dedicated to linear circuits it can be adapted to multiple soft fault diagnosis of nonlinear ones. It is illustrated by an example of a CMOS circuit designed in a sub-micrometre technology.
Rocznik
Strony
331--346
Opis fizyczny
Bibliogr. 42 poz., rys., tab., wykr., wzory
Twórcy
  • Lodz University of Technology, Faculty of Electrical, Electronic, Computer and Control Engineering, Stefanowskiego 18/22, 90-924 Łódź, Poland
autor
  • Lodz University of Technology, Faculty of Electrical, Electronic, Computer and Control Engineering, Stefanowskiego 18/22, 90-924 Łódź, Poland
Bibliografia
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  • [3] Bhunia, S., Raychowdhury, A., Roy, K. (2005). Defect oriented testing of analog circuits using wavelet analysis of dynamic supply current. J. Electron Test., 21, 147-159.
  • [4] Catelani, M., Fort, A. (2002). Soft fault detection and isolation in analog circuits: some results and a comparison between a fuzzy approach and radial basis function networks. IEEE Trans. Instrum. Meas., 51, 196-202.
  • [5] Czaja, Z., Zielonko, R. (2004). On fault diagnosis of analogue electronic circuits based on transformations in multi-dimensional spaces. Measurement, 35, 293-301.
  • [6] Czaja, Z. (2008). Using a square-wave signal for fault diagnosis of analog parts of mixed-signal electronic embedded systems. IEEE Trans. Instrum. Meas., 57, 1589-1595.
  • [7] Dai, H., Souders, T.M. (1990). Time-domain testing strategies and fault diagnosis for analog systems. IEEE Trans. Instrum. Meas., 19, 157-162.
  • [8] Deng, Y., Shi, Y., Zhang, W. (2012). An approach to locate parametric faults in nonlinear analog circuits. IEEE Trans. Instrum. Meas., 61, 358-367.
  • [9] Fedi, G., Manetti, S., Piccirilli, M.C., Starzyk, J. (1999). Determination of an optimum set of testable components in the fault diagnosis of analog linear circuits. IEEE Trans. Circ. Syst.-I, 46, 779-787.
  • [10] Gizopoulos, D. (2006). Advances in electronic testing. Challenges and methodologies. Springer, Dordrecht.
  • [11] Grasso, F., Luchetta, A., Manetti, S., Piccirilli, M.C. (2007). A method for the automatic selection of test frequencies in analog fault diagnosis. IEEE Trans. Instrum. Measur., 56, 2322-2329.
  • [12] Grzechca, D. (2011). Soft fault clustering in analog electronic circuits with the use of self organizing neural network. Metrol. Meas. Syst., 18(4), 555-568.
  • [13] Grzechca, D. (2015). Construction of an expert system based on fuzzy logic for diagnosis of analog electronic circuits. Int. J. Electron. Telecomm., 61, 77-82.
  • [14] Han H., Wang H., Tian S., Zhang N. (2013). A new analog circuit fault diagnosis method based on improved Mahalanobis distance. J. Electron Test., 29, 95-102.
  • [15] Hałgas, S., Tadeusiewicz, M. (2008). Multiple soft fault diagnosis of analogue electronic circuits. Procceedings of the International Conference on Signals and Electronic Systems ICSES’2008, Kraków, Poland, 533-536.
  • [16] Jahangiri, M., Razaghian, F. (2014). Fault detection in analogue circuits using hybrid evolutionary algorithm and neural network. Analog Int. Cir. Sig. Proc., 80, 551-556.
  • [17] Jantos, P., Grzechca, D., Rutkowski. J. (2012). Evolutionary algorithms for global parametric fault diagnosis in analogue integrated circuits. Bull. Polish Acad. Scien., 60, 133-142.
  • [18] Jiang Y., Wang Y., Luo H. (2015). Fault diagnosis of analog circuit based on a second map SVDD. Analog Int. Cir. Sig. Proc., 85, 395-404.
  • [19] Kabisatpathy, P., Barua, A., Sinha, S. (2005). Fault diagnosis of analog integrated circuits. Springer, Dordrecht.
  • [20] Long, B., Li, M., Wang, H., Tian, S. (2013). Diagnostics of analog circuits based on LS_SVM using time-domain features. Circuits Syst. Signal Process., 32, 2683-2706.
  • [21] Materka, A., Strzelecki, M. (1996). Parametric testing of mixed-signal circuits by ANN processing of transient responses. J. Electron Test., 9, 187-202.
  • [22] Papakostas, D.K., Hatzopoulos, A.A. (2008). A unified procedure for fault detection of analog and mixed-mode circuits using magnitude and phase components of the power supply current spectrum. IEEE Trans. Instrum. Measur., 57, 2589-2995.
  • [23] Papakostas D.K., Hatzopoulos A.A. (2010). Improved analogue fault coverage estimation using probability analysis. Int. J. Circ. Theory Appl., 38, 503-514.
  • [24] Robotycki, A., Zielonko, R. (2002). Fault diagnosis of analog piecewise linear circuits based on homotopy. IEEE Trans. Instrum. Meas., 51, 867-881.
  • [25] Sałat, R., Osowski, S. (2011). Support Vector Machine for soft fault location in electrical circuits. J. Intelligent Fuzzy Systems., 22, 21-31.
  • [26] Sindia, S., Agrawal, V.D,. Singh, V. (2012). Parametric fault testing of non-linear analog circuits based on polynomial and V-transform coefficients. J. Electron Test., 28, 757-771.
  • [27] Tadeusiewicz, M., Korzybski, M. (2000). A method for fault diagnosis in linear electronic circuits. Int. J. Circ. Theory Appl., 28, 245-262.
  • [28] Tadeusiewicz, M., Hałgas, S., Korzybski, M. (2002). An algorithm for soft-fault diagnosis of linear and nonlinear circuits. IEEE Trans. Circ. Syst.-I, 49, 1648-1653.
  • [29] Tadeusiewicz, M., Hałgas, S. (2006). An algorithm for multiple fault diagnosis in analogue circuits. Int. J. Circ. Theory Appl., 34, 607-615.
  • [30] Tadeusiewicz, M., Hałgas, S. (2015). A new approach to multiple soft fault diagnosis of analog BJT and CMOS circuits. IEEE Trans. Instrum. Measur., 64, 2688-2695.
  • [31] Tadeusiewicz, M., Kuczyński, A., Hałgas, S. (2015). Catastrophic fault diagnosis of a certain class of nonlinear analog circuits. Circuits Syst. Signal Process., 34, 353-375.
  • [32] Tadeusiewicz, M., Hałgas, S. (2016). Multiple soft fault diagnosis of DC analog CMOS circuits designed in nanometer technology, Analog Int. Cir. Sig. Proc., 88, 65-77.
  • [33] Tadeusiewicz, M., Hałgas, S. (2016). Diagnosis of soft spot short defects in analog circuits considering the thermal behaviour of the chip. Metrol. Meas. Syst., 23(2), 239-250.
  • [34] Xie, Y., Li, X., Xie, S., Xie, X., Zhou, Q. (2014). Soft fault diagnosis of analog circuits via frequency response function measurements. J. Electron Test., 30, 243-249.
  • [35] Yang, C., Tian, S., Long, B., Chen, F. (2011). Methods of handling the tolerance and test-point selection problem for analog-circuit fault diagnosis. IEEE Trans. Instrum. Meas., 60, 176-185.
  • [36] Yu, W., He, Y. (2015). Analog circuit fault diagnosis via sensitivity computation. J. Electron Test., 31, 119-122.
  • [37] Yuan, L., He, Y., Huang, J., Sun, Y. (2010). A new neural-network-based fault diagnosis approach for analog circuits by using kurtosis and entropy as a preprocessor. IEEE Trans. Instrum. Meas., 59, 586-595.
  • [38] Zhou, Q.Z., Xie, Y.L., Li, X.F., Bi, D.J., Xie, X., Xie, S.S. (2014). Methodology and equipments for analog circuit parametric faults diagnosis based on matrix eigenvalues. IEEE Trans. Appl. Superconductivity, 24, 1-6.
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Uwagi
EN
1. This work was supported in part by Polish Ministry of Science and Higher Education under Grant DIR/WK/2016/03 and in part by the Statutory Activities of Lodz University of Technology 5418DzS.
PL
2. Opracowanie rekordu w ramach umowy 509/P-DUN/2018 ze środków MNiSW przeznaczonych na działalność upowszechniającą naukę (2018).
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-c56ca7d8-e0d5-4657-bf75-b5a38505465e
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