Analysis and Design of a Chopped Current Mode Instrumentation Amplifier

• Autorzy: Voulkidou A , Siskos S , Laopoulos T
• Języki publikacji: EN

Abstrakty

EN

This paper presents the design of a chopper stabilized current mode instrumentation amplifier and analyzes the performance limitations imposed by chopping technique in detail. The amplifier targets to be the read out circuitry of a high precision temperature sensor. Since the required bandwidth in this kind of applications is very low, nested chopping technique is used to provide continuous offset reduction and eliminate 1/f noise. The amplifier is designed in 0.18 μm CMOS process. The resulting input referred noise is 20 nV/√ Hz, the offset is 582 nV and the CMRR exceeds 110 dB. The power consumption of the total design is 420 μW.

Słowa kluczowe

EN

current mode instrumentation amplifier; nested chopping; chopping improvements

PL

wzmacniacz pomiarowy; tryb prądowy; chopping

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2013
• Tom: Vol. 4, nr 1
• Strony: 6--11
• Opis fizyczny: Bibliogr. 14 poz.

Twórcy

autor

Voulkidou A

• Electronics Laboratory of Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece

autor

Siskos S

• Electronics Laboratory of Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece

autor

Laopoulos T

• Electronics Laboratory of Physics Department, Aristotle University of Thessaloniki, Thessaloniki, Greece

Bibliografia

• [1] J.H. Nielsen and T. Lehmann, An implamentable CMOS amplifier for nerve signals , Analog Int Circ. Signal Proc., vol.36, pp.153-164, Lyly - Aug., 2003.
• [2] J. Szynowski, CMRR anlysis in instrumentation amplifier , Electron. Lett., vol.19, no. 14, pp. 547-549, 1983.
• [3] R.P. Areny and J.G. Webster, Common-mode rejection ratio in differential amplifier stages , IEEE Trans. Instrum. Meas., vol. 40, no. 4, pp. 669-676, Aug.1991.
• [4] S. J. Azhari and H. Fazalipoor, A novel current-mode instrumentation amplifier (CMIA) topology , IEEE Trans. Instrum. Meas., vol. 49, no. 6, pp. 1272-1277, Dec. 2000.
• [5] S. J. G. Gift, An enchanced current-mode instrumentation amplifier , IEEE Trans. Instrum. Meas., vol. 50, no. 1, pp. 85-88, Jan. 2001.
• [6] K. Koli and K. A. I. Halonen, CMRR enchanced techniques for current-mode instrumentation amplifiers , IEEE Trans. Circuits Syst., vol. 47, no. 5, pp. 622-632, 2000.
• [7] D. Johns and K. Martin, Analog Integrated Circuit Design , Wiley: New York, NY, 1997.
• [8] A. Baker , K. Thiele and J. H. Hustijsing, A CMOS nested chopper instrumentation amplifier with 100nV offset , IEEE J. of Solid State Circuits, vol.35, pp. 1877-1883, 2000.
• [9] J. H. Nielsen and E. Bruun, A CMOS low-noise instrumentation amplifier using chopper modulation , Analog Integr. Circuits and Signal Proc., vol 42, pp. 65-76, 2005.
• [10] C. C. Enz and G.C. Temew, Circuit techniques for reducing the effects of opamp imperfections: autozeroing, correlated double sampling, and chopper stabilization , Circuits and Systems, IEEE Transactions on, pp.256-264,Feb 1990.
• [11] Guggenbhl and Walter, On charge injection in analog MOS switches and dummy switch compensation techniques , Circuits and Systems, IEEE Transactions on, pp.256-264,Feb 1990.
• [12] Wilson, Recent developments in current conveyors and current mode circuits , Proc.IEEE, vol. 135, no. 2, pp.63-77, April 1990.
• [13] F. Qinwen, F. Sebastiano, H. Huijsing, K. Makinwa, A 1.8W 1V-offset capacitively-coupled chopper instrumentation amplifier in 65nm CMOS , Proc. of ESSCIRC 2010, pp.170-173, 14-16 Sept. 2010.
• [14] M.A.P. Pertijs and W.J. Kindt, A 140 dB-CMRR Current-Feedback Instrumentation Amplifier Employing Ping-Pong Auto-Zeroing and Chopping , IEEE J. of Solid-State Circuits, vol.45, no. 10, pp.2044-2056, Oct. 2010.