Java Based Transistor Level CPU Simulation Speedup Techniques

• Autorzy: Wojtowicz T.

Identyfikatory

DOI

10.4467/20838476SI.16.016.4357

• Języki publikacji: EN

Abstrakty

EN

Transistor level simulation of the CPU, while very accurate, brings also the performance challenge. MOS6502 CPU simulation algorithm is analysed with several optimisation techniques proposed. Application of these techniques improved the transistor level simulation speed by a factor of 3–4, bringing it to the levels on par with fastest RTL-level simulations so far.

Słowa kluczowe

EN

CPU; microarchitecture; simulation; registers; pipeline; activity; 6502

• Wydawca: Wydawnictwo Uniwersytetu Jagiellońskiego
• Czasopismo: Schedae Informaticae
• Rocznik: 2015
• Tom: Vol. 24
• Strony: 179--195
• Opis fizyczny: Bibliogr. 13 poz., rys.

Twórcy

autor

Wojtowicz T.

• Department of Computer Sciences and Computer Methods, Pedagogical University ul. Podchorążych 2, 30-084 Kraków, Poland

Bibliografia

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