Implementing Cyclic Redundancy Check as Error Correction Technique in HDLC

• Autorzy: Sooch Shardeep Kaur , Gupta Meenu , Kumar Rakesh

Identyfikatory

DOI

10.15439/2020KM13

• Konferencja: International Conference on Research in Management & Technovation (05-06.12.2020 ; Nagpur, Indie)
• Języki publikacji: EN

Abstrakty

EN

Any successful communication is governed by some set of rules to manage the flow control of the transmitted data. One such protocol is High-level Data Link Control (HDLC) which is a bit-oriented protocol used for communication over the point to point or multipoint links. Residing in the data link layer (layer 2) of Open System Interconnection (OSI), this protocol transmits data in frames. HDLC can be used for detecting the errors in the data which are induced during the transmission from sender to receiver. This paper focuses on not only detecting the error but also correcting it by using Cyclic Redundancy Check (CRC). Cyclic codes are a special type of linear Block Codes in which one codeword can be cyclically shifted to obtain another codeword. The CRC generator is modulo-2 added with the data in the information frame of HDLC and the remainder is obtained. When this data is sent over any transmission channel, there are high chances of data being erroneous due to interference of unrequired signals in the channel. When data reaches the receiver end, a similar modulo-2 addition is carried to obtain another remainder. This remainder is compared with the remainder transmitted by the sender. The two compared remainders detect the location of the error bit which is corrected by flipping that specific bit. This reduces the need for Automatic Repeat Request (ARQ) mechanisms to obtain the correct information as the data can be self-corrected at the receiver end.

Słowa kluczowe

EN

HDLC; High-Level Data Link Control; frame check sequence; cyclic redundancy check; Xilinx; automatic repeat reques

PL

HDLC; sekwencja kontroli ramek; cykliczna kontrola nadmiarowości; Xilinx; automatyczne żądanie powtórzenia

• Wydawca: Polskie Towarzystwo Informatyczne
• Czasopismo: Annals of Computer Science and Information Systems
• Rocznik: 2020
• Tom: Vol. 24
• Strony: 131--136
• Opis fizyczny: Bibliogr. 17 poz., tab., rys.

Twórcy

autor

Sooch Shardeep Kaur

• Chandigarh University Punjab, India

autor

Gupta Meenu

• Chandigarh University Punjab, India

autor

Kumar Rakesh

• Chandigarh University Punjab, India

Bibliografia

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• 5. Priyanka Mishra, “Study and Performance Evaluation of Xilinx HDLC Controller and FCS Calculator”, IOSR Journal of Engineering, Nov 2012
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• 7. Gaurav Chandil, Priyanka Mishra, “Design and Implementaion of HDLC Controller Using CRC-16”, IJMER Vol. 3 , 2012.
• 8. V.M. Ramaa Priyaa, “Error Detection and Correction In Encoder and Decoder for Nanmemory”, IJAREEIE, Vol 2, June 2013
• 9. Narinder Pal Singh, Sukhjit Singh, “RAM Error Detection and Correction using HVD implementation”, European Scientific Journal , Nov 2013
• 10. Mostafa Kishani, Hamid R. Zarandi, Hossein Pedram, Alireza Tajary, Mohsen Raji, Behnam Ghavami, “HVD: horizontalvertical-diagonal error detecting and correcting code to protect against with soft errors", Design Automation for embedded systems, April 2011
• 11. Shubham Fadnavis, “An HVD based error detection and correction code in HDLC Protocol used for communication”, IJARCCE, Vol 2, Issue 6, 2013
• 12. Anil Kumar Singh, “Error Detection and correction by hamming code”, ICGTSPICC, June 2017
• 13. Robbi Rahim, “Bit Error Detection and Correction with Hamming Code Algorithm”, IJSRSET, Vol. 3, 2017.
• 14. Varinder Singh and Narinder Sharma,“Improving Performance Parameters of Error Detection and Correction in HDLC Protocol by using Hamming Method”, International Journal of Computer Applications, Vol 12, Sept 2015
• 15. Michael O. Ezea, “Performance Analysis of CRC Error detection technqiue in the Wireless Sensor Network”, International Research Journal of Engineering and Technology, Vol-7, June 2020.
• 16. Giuliano Benelli,“ARQ Protocols for High Efficieny Digital Communication Systems”, IETE Journal of Research, June 2015
• 17. Pramod S P, Akshay S kotain, Rajagopal A, “FPGA implementation of one and two bit error correction using CRC”, International conference on recent trends in computer science and engineering 2012.

Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).