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Performance analysis of SRF PLL type-3 with dynamic feed forward frequency estimator for abnormal grid conditions

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
A phase-locked loop (PLL) is a closed-loop feedback control device that synchronizes its output signal with an input signal in both frequency and time. This paper presents a robust method for tracking against adverse conditions of the fundamental sequence component of utility voltage. The proposed phase-locked loop (PLL) is a hybrid configuration of the phase- locked loop type-3 (SRF type-3) synchronous reference frame coupled with a feed-forward frequency estimator using a selective harmonic filtering technique. A SRF type -2 based PLL has a secondary closed path. Under the ramp frequency transition, it has a steady-state step and a frequency error. In the proposed PLL, the constant gain loop filter is used to eliminate the phase and frequency error. Feed-forward operation with selective harmonic pre-filtering enables fast-tracking with a low tracking error of the reference signal. From the results it is evident that the proposed PLL achieves a high bandwidth and quick dynamic response without endangering the stability and filtering capability. The proposed system has been tested through MATLAB Simulink platform under abnormal conditions.
Rocznik
Strony
87--95
Opis fizyczny
Bibliogr. 26 poz., rys., tab., wykr.
Twórcy
  • Rajasthan Technical University Kota
  • Indian Institute of Technology Roorkee
  • Rajasthan Technical University Kota
Bibliografia
  • 1. Surprenant, M., Hiskens, I., and Venkataramanan, G. (2011) Phase locked loop control of inverters in a microgrid. 2011 IEEE Energy Conversion Congress and Exposition.
  • 2. Kim, Y.-H., Kim, K.-S., Kwon, B.-K., and Choi, C.-H. (2008) A fast and robust PLL of MCFC PCS under unbalanced grid voltages. 2008 IEEE Power Electronics Specialists Conference.
  • 3. Saidu, M.M., Jaiswal, S.P., Jayaswal, K., Mitra, S., and Bhadoria, V.S. (2020) A survey on: Automation of micro grid and micro distributed generation. Materials Today: Proceedings.
  • 4. Jain, S.R., Ravikirthi, P., and Chilakapati, N. (2014) A Novel Self-Consistent Model Based Optimal Filter Design for the Improved Dynamic Performance of 3-phase PLLs for Phase Tracking Under Grid Imperfections. Journal of Control Automation and Electrical Systems, 25 (5), 620-628.
  • 5. Chaoui, H., Okoye, O., and Khayamy, M. (2016) Grid Synchronization Phase-Locked Loop Strategy for Unbalance and Harmonic Distortion Conditions. Journal of Control Automation and Electrical Systems, 27 (4), 463-471.
  • 6. Timbus, A.V., Teodorescu, R., Blaabjerg, F., Liserre, M., and Rodriguez, P. PLL Algorithm for Power Generation Systems Robust to Grid Voltage Faults. 37th IEEE Power Electronics Specialists Conference.
  • 7. Escobar, G., Martinez-Montejano, M.F., Valdez, A.A., Martinez, P.R., and Hernandez-Gomez, M. (2011) Fixed-Reference-Frame Phase-Locked Loop for Grid Synchronization Under Unbalanced Operation. IEEE Transactions on Industrial Electronics, 58 (5), 1943-1951.
  • 8. Kulkarni, A., and John, V. (2015) Design of synchronous reference frame phase-locked loop with the presence of dc offsets in the input voltage. IET Power Electronics, 8 (12), 2435-2443.
  • 9. Huajun, Z., Yixin, S., Danhong, Z., Jun, Z., Rui, C., Jiazheng, P., and Lili, W. (2015) The optimization of controller parameters for three phases PLL tracking system. 2015 Chinese Automation Congress (CAC).
  • 10. Freijedo, F.D., Doval-Gandoy, J., Lopez, O., and Acha, E. (2009) Tuning of Phase-Locked Loops for Power Converters Under Distorted Utility Conditions. IEEE Transactions on Industry Applications, 45 (6), 2039-2047.
  • 11. Han, Y., Luo, M., Chen, C., Jiang, A., Zhao, X., and Guerrero, J.M. (2016) Performance Evaluations of Four MAF-Based PLL Algorithms for Grid-Synchronization of Three-Phase Grid-Connected PWM Inverters and DGs. Journal of Power Electronics, 16 (5), 1904-1917.
  • 12. Liccardo, F., Marino, P., and Raimondo, G. (2011) Robust and Fast Three-Phase PLL Tracking System. IEEE Transactions on Industrial Electronics, 58 (1), 221-231.
  • 13. Awad, H., Svensson, J., and Bollen, M.J. (2005) Tuning Software Phase-Locked Loop for Series-Connected Converters. IEEE Transactions on Power Delivery, 20 (1), 300-308.
  • 14. Meena, K., Jayaswal, K., and Palwalia, D.K. (2020) Analysis of Dual Active Bridge Converter for Solid State Transformer Application using Single-Phase Shift Control Technique. 2020 International Conference on Inventive Computation Technologies (ICICT).
  • 15. Gupta, N., Singh, S.P., Dubey, S.P., and Palwalia, D.K. (2012) Digital Signal Processor based Performance Investigation of Indirect Current Controlled Active Power Filter for Power Quality Improvement. International Journal of Emerging Electric Power Systems, 13 (2).
  • 16. Institutional Repository @ IITR: Fuzzy logic controlled three-phase three-wired shunt active power-filter for power quality improvement.
  • 17. Research on emergency DC power support coordinated control for hybrid multi-infeed HVDC system - Archives of Electrical Engineering - PAS Journals Repository.
  • 18. Seema Agrawal, D.K.P., Seemant Chourasiya (2020) Performance Measure of Shunt Active Power Filter Applied with Intelligent Control Technique. Journal of Power Technologies, 100.
  • 19. Lee, S., Lee, J.-H., and Cha, H. (2011) Grid synchronization PLL robust to frequency variation unbalanced and distorted voltage. 2011 IEEE Energy Conversion Congress and Exposition.
  • 20. Golestan, S., Ramezani, M., and Guerrero, J.M. (2014) An Analysis of the PLLs With Secondary Control Path. IEEE Transactions on Industrial Electronics, 61 (9), 4824-4828.
  • 21. Kamata, M., Shono, T., Saba, T., Sasase, I., and Mori, S. Third-order phase-locked loops using dual loops with improved stability. 1997 IEEE Pacific Rim Conference on Communications Computers and Signal Processing, PACRIM. 10 Years Networking the Pacific Rim, 1987-1997.
  • 22. Golestan, S., Monfared, M., Freijedo, F.D., and Guerrero, J.M. (2013) Advantages and Challenges of a Type-3 PLL. IEEE Transactions on Power Electronics, 28 (11), 4985-4997.
  • 23. Karimi-Ghartemani, M., Ooi, B.-T., and Bakhshai, A. (2011) Application of Enhanced Phase-Locked Loop System to the Computation of Synchrophasors. IEEE Transactions on Power Delivery, 26 (1), 22-32.
  • 24. Mchida, H., Kambara, M., Tanaka, K., and Kobayashi, F. (2010) A motor speed control system using dual-loop PLL and speed feed-forward/back. 2010 IEEE International Conference on Mechatronics and Automation.
  • 25. (2009) A PWM motor speed control system based on the dual-loop PLL. 2009 ICCAS-SICE.
  • 26. Agrawal, S., and Palwalia, D.K. (2019) A modernistic PLL based on feed forward frequency estimator with selective harmonic prefilter for grid imperfection. International Journal of Power and Energy Conversion, 10 (3), 350.
Uwagi
PL
Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).
Typ dokumentu
Bibliografia
Identyfikator YADDA
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