Physical Implementation and Testing of Low-Power Adiabatic Flip-Flops with Energy-Recycling Pads

• Autorzy: Jiang J. , Hu J.

Warianty tytułu

PL

Implementacja i testy przerzutnika diabatycznego małej mocy z blokiem odzyskiwania energii

• Języki publikacji: EN

Abstrakty

EN

This paper presents adiabatic flip-flops based on CPAL (complementary pass-transistor adiabatic logic) circuits with energy-recycling output pad cells. The energy-recycling output pad cells for driving adiabatic chips include mainly bonding pads, ESD (electrostatic discharge) protection circuits, and two stage energy-recycling buffers. The adiabatic flip-flops and sequential circuits with energy-recycling output pad cells have been fabricated with Chartered 0.35um process. The adiabatic flip-flops have large energy savings over a wide range of frequencies.

PL

W artykule zaproponowano adiabatyczny przerzutnik bazujący na układach CPAL – complementary pass-transistor adiabatic logic). Zastosowano też blok wyjściowy z odzyskiwaniem energii.

Słowa kluczowe

EN

adiabatic; computing; flip-flop; energy recycling

PL

przerzutnik diabatyczny; odzyskiwanie energii; implementacja

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2012
• Tom: R. 88, nr 9b
• Strony: 192--195
• Opis fizyczny: Bibliogr. 9 poz., rys.

Twórcy

autor

Jiang J.

• Ningbo University

autor

Hu J.

• Ningbo University

Bibliografia

• [1] Zhang W. Q., Su L., Zhang Y., Li L. F., Hu J. P., Low-leakage flip-flops based on dual-threshold and multiple leakage reduction techniques, Journal of Circuits, Systems and Computers, 20 (2011), No. 1, 147-162.
• [2] Hu J. P. , Xu T. F., Li H., A lower-power register file based on complementary pass-transistor adiabatic logic, IEICE Trans. on Inf. & Sys., E88–D (2005), No. 7, 1479–1485
• [3] Maksimovic D., Oklobdzija V. G., Nikolic B., Current K. W., Clocked CMOS adiabatic logic with integrated single-phase power-clock supply, IEEE Trans. on VLSI, 8 (2000), No. 4, 460-463.
• [4] Kim S., Papaefthymiou M. C., True single-phase adiabatic circuitry, IEEE Tran. on VLSI Systems, 9(2001), No. 1, 52-63
• [5] Zhang W. Q., Zhou D., Hu X. Y., Hu J. P., The implementations of adiabatic flip-flops and sequential circuits with power-gating schemes, in Proc. IEEE MWSCAS, 2007. pp. 767-770
• [6] Ker M. D., Chen S. H., Chuang C. H., ESD failure mechanisms of analog I/O cells in 0.18-μm CMOS technology, IEEE Trans on device and materials reliability, 6 (2006), No. 1, 102-111
• [7] Daniel S., Krieger G., Process and design optimization for advanced CMOS I/O ESD protection devices, in Proc. EOS/ESD, 1990, pp.206–213
• [8] Ker M. -D., Chen T. -Y., Wu C. -Y., Chang H. -H., ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications, IEEE J. Solid- State Circuits, 35(2000), No. 8, 1194–1199
• [9] Hu J. P., Yu X. Y., Low voltage and low power pulse flip-flops in nanometer CMOS processes, Current Nanoscience, 8 (2012), No. 1, 102-107.