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A 400 fJ per-cycle frequency reference for internet of things

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Warianty tytułu
Języki publikacji
EN
Abstrakty
EN
This work presents an ultra-low power oscillator designed to target different contexts, such as crystal-assisted timekeeping, reference oscillator to optimize the always on domain of a microcontroller or wake-up timer. This oscillator enables ultralow power operation in 0.18 μm CMOS technology; the core oscillator consumes 2.5 nW at room temperature, with a temperature stability of 14 ppm/°C [-40°C - 60°C] and 0.07 %/V supply sensitivity.
Rocznik
Strony
41--46
Opis fizyczny
Bibliogr. 20 poz., il. kolor., rys., wykr.
Twórcy
autor
  • Institute of Electrical Engineering (IEL), École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland
  • Institute of Electrical Engineering (IEL), École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland
autor
  • EM Microelectronic-Marin SA, Rue des Sors 3, 2074 Marin-Epagnier, Switzerland
autor
  • Institute of Electrical Engineering (IEL), École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland
Bibliografia
  • [1] D. Lanfranchi, E. Dijkstra, and D. Aebischer, “A microprocessor-based analog wristwatch chip with 3 seconds/year accuracy,” in Proceedings of IEEE International Solid-State Circuits Conference - ISSCC ’94, 1990, vol. 23, no. 3, pp. 92–93.
  • [2] E. a. Vittoz, M. G. R. Degrauwe, and S. Bitz, “High-Performance Crystal Oscillator Circuits: Theory and Application.,” IEEE J. SolidState Circuits, vol. 23, no. 3, pp. 774–783, 1987.
  • [3] H. G. Barrow, T. L. Naing, R. a. Schneider, T. O. Rocheleau, V. Yeh, Z. Ren, and C. T. C. Nguyen, “A real-time 32.768-kHz clock oscillator using a 0.0154-mm 2 micromechanical resonator frequency-setting element,” 2012 IEEE Int. Freq. Control Symp. IFCS 2012, Proc., pp. 277–282, 2012.
  • [4] U. Denier, “Analysis and design of an ultralow-power CMOS relaxation oscillator,” IEEE Trans. Circuits Syst. I Regul. Pap., vol. 57, no. 8, pp. 1973–1982, 2010.
  • [5] S. Jeong, I. Lee, D. Blaauw, and D. Sylvester, “Timer Using a Constant Charge Subtraction Scheme,” pp. 3–6, 2014.
  • [6] K. J. Hsiao, “A 32.4 ppm/°C 3.2-1.6V self-chopped relaxation oscillator with adaptive supply generation” IEEE Symp. VLSI Circuits, Dig. Tech. Pap., no. 1, pp. 14–15, 2012.
  • [7] M. Grözing and M. Berroth, “Reduction of CMOS Inverter Ring Oscillator Close-In Phase Noise by Current Mode Instead of Voltage Mode Supply” pp. 97–100, 2006.
  • [8] P. Nugroho, E. Leelarasmee, and N. Fujii“Tuning Analysis of a CMOS Current Controlled Ring Oscillator,” pp. 49–52, 2006.
  • [9] K. Sundaresan, P. E. Allen, and F. Ayazi, “Process and temperature compensation in a 7-MHz CMOS clock oscillator,” IEEE J. Solid-State Circuits, vol. 41, no. 2, pp. 433–441, 2006.
  • [10] A. Shrivastava and B. H. Calhoun, “A 150nW, 5ppm/??C, 100kHz onchip clock source for ultra low power SoCs,” Proc. Cust. Integr. Circuits Conf., pp. 12–15, 2012.
  • [11] D. Ruffieux, F. Krummenacher, A. Pezous, and G. Spinola-Durante, “Silicon resonator based 3.2 ȝw real time clock with ±10 ppm frequency accuracy,” IEEE J. Solid-State Circuits, vol. 45, no. 1, pp. 224–234, 2010.
  • [12] R. Schober, I. Opris, F. Krummenacher, “HIGH SENSITIVITY RFID TAG INTEGRATED CIRCUITS,” WO/2007/014053, 2007.
  • [13] S. Docking and M. Sachdev, “A method to derive an equation for the oscillation frequency of a ring oscillator,” IEEE Trans. Circuits Syst. I Fundam. Theory Appl., vol. 50, no. 2, pp. 259–264, Feb. 2003.
  • [14] U. Guler and G. Dundar, “Modeling phase noise and jitter in subthreshold region and assessing the randomness performance of CMOS ring oscillators,” in 2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012, vol. 0, no. 3, pp. 257–260.
  • [15] R. M. Swanson and J. D. Meindl, “Ion implanted CMOS transistors in low voltage circuits,” Jssc, no. 2, pp. 1–8, 1999.
  • [16] M. G. Degrauwe, J. Rijmenants, E. A. Vittoz, and H. J. De Man, “Adaptive biasing CMOS amplifiers,” IEEE J. Solid-State Circuits, vol. 17, no. 3, pp. 522–528, 1982.
  • [17] R. Muller, H.-J. Pfleiderer, and K.-U. Stein, “Energy per logic operation in integrated circuits: definition and determination,” IEEE J. Solid-State Circuits, vol. 11, no. 5, pp. 657–661, Oct. 1976.
  • [18] H. Asano, T. Hirose, K. Tsubaki, T. Miyoshi, T. Ozaki, N. Kuroki, and M. Numa, “A 1.66-nW/kHz, 32.7-kHz, 99.5ppm/°C fully integrated current-mode RC oscillator for real-time clock applications with PVT stability,” in ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 2016, vol. 2, pp. 149–152.
  • [19] P. M. Nadeau, A. Paidimarri, and A. P. Chandrakasan, “Ultra LowEnergy Relaxation Oscillator With 230 fJ/cycle Efficiency,” IEEE J. Solid-State Circuits, vol. 51, no. 4, pp. 789–799, 2016.
  • [20] A. Shrivastava and B. H. Calhoun, “A 150nW, 5ppm/??C, 100kHz onchip clock source for ultra low power SoCs,” in Proceedings of the Custom Integrated Circuits Conference, 2012, pp. 12–15.
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-b4acad6d-fef7-4546-badb-03e94d894773
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