PLC implementation in the form of a System-on-a-Chip

• Autorzy: Mazur P. , Czerwinski R. , Chmiel M.

Identyfikatory

DOI

10.24425/bpasts.2020.135386

• Języki publikacji: EN

Abstrakty

EN

The aim of the paper is to present the implementation of a PLC designed in the form of a System-on-a-Chip. The presented PLC is compatible with the IEC61131‒3 standard. More precisely, the Instruction List language is the native language of the designed CPU, so there is no need for multiple language transformations. In the proposed solution each instruction of the CPU program written in Instruction List is directly translated to machine code. The designed CPU is capable of performing logic operations up to 32-bit Boolean data types. However, the developed CPU is very flexible due to its architecture: data memory can be addressed as bit/byte/word/dword. Moreover, diverse blocks such as timers, counters, and hardware acceleration blocks, can be connected to the CPU by means of an APB AMBA bus. The designed PLC has been implemented in an FPGA device and can be used in cyber-physical systems and Industry 4.0.

Słowa kluczowe

EN

PLC; FPGA; AMBA; APB; IEC 61131-3

PL

PLC; FPGA; AMBA; APB; IEC 61131-3

• Wydawca: Polska Akademia Nauk, Wydział IV Nauk Technicznych
• Czasopismo: Bulletin of the Polish Academy of Sciences. Technical Sciences
• Rocznik: 2020
• Tom: Vol. 68, nr 6
• Strony: 1263--1273
• Opis fizyczny: Bibliogr. 29 poz., rys., tab.

Twórcy

autor

Mazur P.

• DisplayLink, ul. Ligocka 103, 40-568 Katowice, Poland

autor

Czerwinski R.

• Silesian University of Technology, Department of Digital Systems, ul. Akademicka 16, 44-100 Gliwice, Poland

autor

Chmiel M.

• Silesian University of Technology, Department of Digital Systems, ul. Akademicka 16, 44-100 Gliwice, Poland

Bibliografia

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Uwagi

Opracowanie rekordu ze środków MNiSW, umowa Nr 461252 w ramach programu "Społeczna odpowiedzialność nauki" - moduł: Popularyzacja nauki i promocja sportu (2021).