Analiza topografii układów scalonych VLSI pod kątem ich produkowalności

Pleskacz W.A., W.A.

Artykuł - szczegóły

Tytuł artykułu

Analiza topografii układów scalonych VLSI pod kątem ich produkowalności

Autorzy

Pleskacz W.A. W.A.

Identyfikatory

Warianty tytułu

Topography analysis of VLSI integrated circuits for manufacturability

Języki publikacji

Abstrakty

W pracy poruszono szereg problemów dotyczących metod analizy topografii układów scalonych wielkiej skali integracji, stosowanych podczas projektowania pod kątem produkowalności (DFM). Położono szczególny nacisk na omówienie znaczenia i sposobów wykorzystania pojęcia obszarów krytycznych topografii masek, jako miary czułości układu scalonego na defekty produkcyjne. Przedstawiono nowy model uzysku produkcyjnego dla układów VLSI. W modelu tym zostały uwzględnione zjawiska nadtrawienia i niedotrawienia warstw, występujące w operacjach litograficznych. Wykazano, że zaniedbanie losowej natury rozrzutów procesu trawienia może prowadzić do powstania znaczącego błędu przy szacowaniu uzysku produkcyjnego. Zaproponowano również metodę szacowania uzysku produkcyjnego dla skalowanych topografii układów scalonych VLSI. Metoda ta umożliwia optymalne skalowanie projektów układów scalonych i pozwala na znaczne zredukowanie czasochłonnych obliczeniowo ekstrakcji funkcji obszarów krytycznych dla przeskalowanych topografii. Ze względu na znaczenie analizy obszarów krytycznych dla metod DFM, w pracy zaprezentowano oryginalny algorytm ekstrakcji obszarów krytycznych na rozwarcia w układach scalonych. W algorytmie tym zostały uwzględnione obszary krytyczne zarówno dla ścieżek przewodzących, jak i dla kontaktów elektrycznych do pozostałych warstw przewodzących. Wprowadzono i omówiono znaczenie nowej koncepcji rejonów kontaktowych dla kontaktów typu Contact Cut i Via. Zaproponowany algorytm umożliwia analizę dużych układów scalonych, w tym układów o topografii różnej od geometrii typu Manhattan. Zademonstrowany przykład analizy rzeczywistej topografii dużego układu scalonego pokazuje, że ekstrakcja obszarów krytycznych dla rozwarć może być wykonana dla przemysłowych układów VLSI w akceptowalnym czasie. Obszerna część pracy została poświęcona zagadnieniu jakości testowania układów scalonych w kontekście metod generacji wektorów testowych, uwzględniających projekt topografii, jak i statystykę występowania defektów produkcyjnych. Przedstawiono metodę charakteryzacji kombinacyjnych komórek standardowych i bloków funkcjonalnych CMOS dla testowania napięciowego i prądowego iddq, opartego na fizycznym modelu uszkodzeń. Zaproponowana metoda umożliwia znalezienie rodzajów defektów, które mogą wystapić w rzeczywistym układzie scalonym, określenie prawdopodobieństwa ich wystąpienia oraz znalezienie wektorów testowych wykrywających te uszkodzenia.

The work raised a number of problems relating to methods of topography analysis of very large scale integrated circuits (IC) used during designing for manufacturability (DFM). Particular emphasis was placed on discussion of the importance and usage of critical areas concept, as a measure of IC layout sensitivity to manufacturing defects. A new manufacturing yield model for VLSI circuits was presented. In this model the phenomenon of over and under etching of the conducting layers, occurring in lithography operations, was taken into account. It has been shown that neglecting the random nature of etching variations can lead to substantial error in yield estimation. The yield estimation approach to layout scaling of VLSI integrated circuit has been proposed as well. This method enables optimal downscaling of the IC design. It also allows to significantly reduce time-consuming extraction of the critical area functions for scaled layouts. Because of the importance of critical areas analysis for DFM methods, the work presents an original algorithm for the extraction of critical areas for opens in integrated circuits. In this algorithm critical areas both for conducting paths and for electrical contacts to the other conducting layers have been considered. The new concept of the Contact/Via contacting regions has been introduced and its relevance has been discussed. The proposed algorithm allows analysis of large ICs and ICs with non-Manhattan geometry. The demonstrated example of realistic layout analysis of a large integrated circuit shows that the extraction of critical areas for opens can be done for industrial VLSI circuits within an acceptable time. An extensive part of the work has been devoted to the issue of integrated circuits testing quality in the context of test vector generation methods taking into account the layout design, as well as manufacturing defect statistics. A characterization methodology of CMOS combinational standard cells and functional blocks for defect based testing and iddq testing has been presented. The proposed methodology allows to find the types of faults that may occur in a real IC, to determine their probabilities, and to find the input test vectors that detect these faults.

Słowa kluczowe

topografia układu scalonego obszar krytyczny uzysk produkcyjny defekty produkcyjne projektowanie pod kątem produkowalności testowanie napięciowe testowanie IDDQ generacja wektorów testowych

integrated circuit layout critical area manufacturing yield manufacturing defects design for manufacturability voltage testing IDDQ testing test vectors generation

Wydawca

Oficyna Wydawnicza Politechniki Warszawskiej

Czasopismo

Prace Naukowe Politechniki Warszawskiej. Elektronika

Rocznik

2009

Tom

z. 172

Strony

3--119

Opis fizyczny

Bibliogr. 154 poz., tab., rys., wykr.

Twórcy

autor

Pleskacz W.A. W.A.

Instytut Mikroelektroniki i Optoelektroniki, Politechnika Warszawska

Bibliografia

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