Novel hardware-efficient design of LMS-based adaptive FIR filter utilizing Finite State Machine and Block-RAM

• Autorzy: Sharifi-Tehrani O.

Warianty tytułu

PL

Sprzętowy projekt filtru adaptacyjnego SOI z mechanizmem FSM

• Języki publikacji: EN

Abstrakty

EN

A novel pure-hardware design of LMS-based adaptive FIR filter core is proposed which is highly efficient in FPGA area/resource utilization and speed. Unlike HW/SW co-design and other pure-hardware methods, the required area/resource is reduced while keeping the speed in an appropriate level by taking advantage of finite state machine (FSM) and using internal block-rams (BRAM). This model because of being completely general (device independent), gives the ability of implementation on different FPGA brands and thus, is suitable for embedded systems, system-onprogrammable- chip (SoPC) and network-on-chip (NoC) applications.

PL

Opisano projekt filtru adapatacyjnego SOI który może byc wykorzystany w technice FPGA. Dla zapewnienia odpowiedniej szybkości zastosowano metodę FSM (finite state machine) i wewnętrzny RAM. Układ może być wykorzystany w systemach typu SoPC (system on programmable chip).

Słowa kluczowe

EN

FPGA; Adaptive FIR Filter; LMS algorithm; embedded system; electrical technology

PL

filtr adaptacyjny; FPGA; elektrotechnika

• Wydawca: Wydawnictwo SIGMA-NOT
• Czasopismo: Przegląd Elektrotechniczny
• Rocznik: 2011
• Tom: R. 87, nr 7
• Strony: 240--244
• Opis fizyczny: Bibliogr. 12 poz., rys., tab., wykr.

Twórcy

autor

Sharifi-Tehrani O.

• Islamic Azad University, Majlesi branch, Young Researches Club,

Bibliografia

• [1] O. Sharifi-Tehrani and M. Ashourian, An FPGA-Based Implementation of ADALINE Neural Network with Low Resource Utilization and Fast Convergence, PRZEGLĄD ELEKTROTECHNICZNY (Electrical Review), 86 (2010), No. 12, 288-292.
• [2] O. Sharifi-Tehrani, M. Ashourian and P. Moallem, An FPGABased Implementation of Fixed-Point Standard-LMS Algorithm with Low Resource Utilization and Fast Convergence, Inter. Rev. on Comp. and Soft. (IReCOS), 5 (2010), No. 4, 436-444.
• [3] V.R. Mustafa, et al., Design and implementation of least mean square adaptive filter on Altera Cyclone II field programmable gate array for active noise control, IEEE Sym. on Industrial Electronics Applications - ISIEA, Kuala Lumpur, Malaysia, (2009), 479-484.
• [4] A. Di Stefano, A. Scaglione and C. Giaconia, Efficient FPGA implementation of an adaptive noise canceller, 7th Inter. Workshop on Computer Architecture for Machine Perception, Italy, (2005), 87-89.
• [5] M. Bahoura and H.Ezzaidi, FPGA-implementation of a sequential adaptive noise canceller using Xilinx system generator, Inter. Conf. on Microelectronics - ICM, Marrakech, (2009), 213-216.
• [6] V. Rodellar, A. Alvarez and E. Martinez, FPGA implementation of an adaptive noise canceller for robust speech enhancement interfaces, 4th Southern Conf. on Programmable Logic, San Carlos de Bariloche, (2008), 13-18.
• [7] H. Zheng-wei and X. Zhi-yuan, Modification of theoretical fixed-point LMS algorithm for implementation in hardware. 2nd Inter. Sym. on Electrical Commerce and Security - ISECS, Vol. 2 China, IEEE Computer Society, USA, (2009), 174-178.
• [8] K.S. Chaitanya, P. Muralidhar and C.C. Rama Rao, Implementation of reconfigurable adaptive filtering algorithms. Inter. Conf. on Signal Processing Systems - ICSPS, Singapore, (2009), 287-291.
• [9] A. Elhossini, S. Areibi and R. Dony, An FPGA implementation of the LMS adaptive filter for audio processing, Intern. Conf. on Reconfigurable Computing and FPGA's, San Luis Potosi, (2006), 1-8.
• [10] A. Jalili, S. G. Boroujeny and M. Eshghi, Design and implementation of a fast active noise control system on FPGA, Mediterranean Conf. on Control & Automation, Athens, (2007), 1-4.
• [11] T. Adali, S. Haykin, Adaptive Signal Processing-Next Generation Solutions, Wiley-IEEE Publication, New York, (2010).
• [12] P.P. Chu, FPGA Prototyping by VHDL Examples, Wiley Publication, New York, (2008).