Oversampling sigma-delta analog-to-digital converters modeling based on VHDL

• Autorzy: Baraniecki R. , Dąbrowski P. , Hejn K.
• Języki publikacji: EN

Abstrakty

EN

The paper presents a VHDL model of an oversampling sigma-delta analog-to-digital converter created on the behavioral hierarchy level. Although VHDL has been primarily devoted to digital circuit design, it can also be applied to certain mixed-signal circuits. The model of the analog part is as simple as possible and includes only necessary parameters that enable to determine the potential resolution of a converter. The model of the digital parttis described in the synthesizable subset of VHDL and parameterized according to the word length and the type of arithmetic applied. The validation process of the converter model is also shown. It is performed by a VHDL simulator and a postprocessor tool enabling to carry out FFT. Simulation results enclosed prove the efficiency of the design approach presented.

Słowa kluczowe

EN

converters; decimator; analog-digital converters; sigma-delta modulator; RTL synthesis; VHDL

PL

konwertory; konwertory analogowo-cyfrowe; modulator sigma-delta; synteza; RTL; VHDL

• Wydawca: Przemysłowy Instytut Elektroniki
• Czasopismo: Prace Przemysłowego Instytutu Elektroniki
• Rocznik: 1998
• Tom: nr 132
• Strony: 163--171
• Opis fizyczny: Bibliogr. 4 poz.,wykr.

Twórcy

autor

Baraniecki R.

autor

Dąbrowski P.

autor

Hejn K.

• Institute of Electron Technology, Al. Lotników 32/46, 02-668 Warsaw, Poland