A design technique for polyphase decimators with binary constrained coefficients for high resolution A/D converters

• Autorzy: Krukowski A. , Kale I. , Morling R. , Hejn K.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a design technique for liigh fidelity multistage decimation filters based on the polyphase and decimator structures presented in [1][2], catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Converter (ADC) applications in excess of 16 bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit tipping algorithm" [3]. This technique is comparatively presented through an example of a cascaded decimation filter, designed for a 20-bit resolution ADC and compared to with other approximation methods. The coefficients and frequency responses of the cascaded filler are reported.

Słowa kluczowe

EN

digital signal processing; analog-digital converters; converters

PL

cyfrowe przetwarzanie sygnałów; konwertory; konwertory analogowo-cyfrowe

• Wydawca: Przemysłowy Instytut Elektroniki
• Czasopismo: Prace Przemysłowego Instytutu Elektroniki
• Rocznik: 1998
• Tom: nr 132
• Strony: 53--56
• Opis fizyczny: Bibliogr. 8 poz., rys., wykr.

Twórcy

autor

Krukowski A.

autor

Kale I.

autor

Morling R.

autor

Hejn K.

• University of Westminster, School of Electronic and Manufacturing System Engineering 115 New Cavendish Street, London WIM & JS, UK