A "bit-flipping" approach to multistage two-path decimation filter design

• Autorzy: Krukowski A. , Kale I. , Cain G. , Hejn K.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a design technique for high fidelity multistage decimation filters based on the polyphase decimator structures presented by Constantinides et al, catering for powers of two sample-rate decreases. The technique is well suited for Analog-to-Digital Convener (ADC) applications in excess of 16-bit resolution. The resulting filter coefficients are constrained to the required bit length using a "bit-flipping algorithm" This technique illustrated in the context of an example of a cascaded decimation filter, designed for a 20-bit resolution ADC. and compared to other approximation methods. The resulting coefficient values and frequency responses of the cascaded filters are reported

Słowa kluczowe

EN

analog-digital converters; digital signal processing

PL

konwertory; konwertory analogowo-cyfrowe; cyfrowe przetwarzanie sygnałów

• Wydawca: Przemysłowy Instytut Elektroniki
• Czasopismo: Prace Przemysłowego Instytutu Elektroniki
• Rocznik: 1998
• Tom: nr 132
• Strony: 42--51
• Opis fizyczny: Bibliogr. 6 poz., rys., wykr.

Twórcy

autor

Krukowski A.

autor

Kale I.

autor

Cain G.

autor

Hejn K.

• University of Westminster, School of Electronic and Manufacturing System Engineering 115 New Cavendish Street, London WIM & JS, UK,