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This paper describes a new design approach for implementing a Polyphase Comb Filter (PCF) based on dispatching input bit-stream and interlaying multiplexer techniques. In order to make our solution more energy efficient in comparison with prior art, we start with a detailed analysis of the drawbacks and advantages of the existing classical techniques. A new structure based on a novel SINC3 design is proposed. This new design uses a controller unit to activate one sub-filter in each specific time interval. As a consequence, no input registers and switches are required. Since this decimation filter is working with a single-bit output bit-stream, the required multiplication function can be simply done by using interlaying multiplexers (MUXs). By interlaying different levels of MUXs along with the navigation of the input bit stream we can easily emulate the multiplication operation. The implementation in a Xilinx Spartan3 FPGA demonstrates the feasibility and hardware efficiency of our solution . The proposed new filter architecture can be readily applicable to any Sigma-Delta (ΣΔ) ADC with a single-bit output stream and it requires a reduced number of adders and registers when compared with the state-of-the-art approaches.
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Tom
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152--158
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Bibliogr. 24 poz.
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- Centre for Technologies and Systems (CTS) at UNINOVA and Dept. of Electrical Engineering (DEE) of the Faculty of Sciences and technology (FCT) at the New University of Lisbon (UNL), Campus da FCT/UNL, 2829-516 Caparica, Portugal, S.Abdollahvand@ieee.org
Bibliografia
- [1] A.Gerosa, and A.Neviani, “A low-power decimation filter for a sigma-delta convertor based on a power-optimised Sinc filter,” in Proc. IEEE Int. Symp. Circuits and Syst. IS CAS 2004, vol. 2, pp. 245–248, May. 2004.
- [2] S. Parameswaran, and N. Krishnapura, “A 100 ?w decimator for a 16 bit 24 kHz bandwidth audio modulator,” in Proc. IEEE Int. Symp. Circuits and Syst. ISCAS 2010, pp. 2410 – 2413, May-June. 2010.
- [3] Y. Gao, L. Jia, and H. Tenhunen, “A fifth-order comb decimation filter for multi-standard transceiver applications,” in Proc. IEEE Int. Symp. Circuits and Syst. ISCAS 2000, vol. 3, pp.89–92, May. 2000.
- [4] Y. Gao, L. Jia, J. Isoaho, and H. Tenhunen, “A comparison design of comb decimators for sigma-delta analog- to-digital converters,” Springer J. Analog Integrated Circuits and Signal Pr ocessing, vol. 22, no.1, pp. 51–60, Jan. 2000.
- [5] E. B. Hougenauer, “An economical class of digital filters for decimation and interpolation,” IEEE Trans. Acoustics, Speech and Signal Processing, vol. 2, no. 2, pp. 155–162, Apr. 1981.
- [6] N. Younis,M. Ashour, and A. Nassar, ”Power-efficient clock/data distribution technique for polyphase comb filter in digital receivers,” IEEE Trans. Circuits and Systems Society, vol. 56, no. 8, pp. 639–643, Aug. 2009.
- [7] M. Abbas, O. Gustafsson, and L. Wanhammar, “Power Estimation of Recursive and Non-Recursive CIC Filters Implemented in Deep- Submicron Technology,” Int. Conf. Gr een Circuits and Systems, ICGCS, pp. 221–225, Jun. 2010.
- [8] F. Yi, and W. Xiaobo, “A novel coefficient automatic calculation method for sinc filter in sigma-delta ADCs,” in Proc. IEEE Asia Pacific Conf. Circuits and Syst. APCCAS 2008, pp. 1240–1243, Dec. 2008.
- [9] E. Dijkstra, O. Nys, C. Piguet, and M. Degrauwe, “On the use of modulo arithmetic comb filters in sigma delta modulators,” Int. Conf. Acoustics, Speech, and Signal Processing, ICASSP-88, vol.4, pp. 2001–2004, Apr. 1988.
- [10] S. R. Norsworthy, R. Schreier, and G. C. Temes, Delta-Sigma Data Converters Theory, Design, and Simulation. New York: IEEE Press, 1997, ch. 13, p. 427.
- [11] X. Liu, “A high speed digital decimation filter with parallel cascaded integrator-comb pre-filters,” 2nd International Congress on Image and Signal Processing, CISP '09, pp. 1–4, Oct. 2009.
- [12] E. Ozalevli, W. Huang, P. E. Hasler, and D. V. Anderson, “A reconfigurable mixed-signal VLSI implementation of distributed arithmetic used for finite-impulse response filtering,” IEEE Trans. Circuits and Systems I, vol. 55, no. 2, pp. 510–521, Mar. 2008.
- [13] H. Aboushady, Y. Dumonteix, M. Louer at, and H. Mehrez, “Efficient polyphased Decomposition of comb decimation filters in analog-to- digital converters,” IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 48, no. 10, pp. 898–903, Oct. 2001.
- [14] N. Y. Ahmed, M. A. Ashour, and A. M. Nassar, “Power efficient polyphase comb decimation filters for modulators in multi-rate digital receivers,”in Proc. European Conf. Circuit Theory and Design, ECCTD 2009, pp. 719–722, Oct. 2009.
- [15] M. Yamada, and A. Nishihara, “High-speed FIR digital filter with CSD coefficients implemented on FPGA,” in Proc. Asia and South Pacific Conf. Design Automation, ASP-DAC 2001, pp. 7–8, 2001.
- [16] A. W. Ruan, Y. B. Liao, P. Li , and J. X. Li, “An ALU-based universal architecture for FIR filters,” Int. Conf. Communications, Circuits and Syst. ICCCAS, pp. 1070–1073, Jul. 2009.
- [17] O. Gustafsson, and H. Ohlsson, “A low power decimation filter architecture for high-speed single-bit sigm a-delta modulation,” in Proc. IEEE Int. Symp. Circuits and Syst. ISCAS 2005, vol. 2, pp. 1453–1456, May 2005.
- [18] P. K. Meher, “New approach to Look-Up-Table design and memory- based realization of FIR digital filter,” IEEE Trans. Circuits and Systems I, vol. 57, no. 3, pp. 592–603, Mar, 2010.
- [19] S. A. White, “Applications of distributed arithmetic to digital signal processing: a tutorial review,” IEEE ASSPN Mag., vol. 6, no. 3, pp. 4–19, Jul. 1989.
- [20] A. Blad, and O. Gustafsson, “Bit-level optimized FIR filter architectures for high-speed decimation app lications,” in Proc. IEEE Int. Symp. Circuits and Syst. ISCAS 2008, pp. 1914–1917, May. 2008.
- [21] O. Gustafssona, J. O. Colemanb, A. G. Dempster, and M.D. Macleod, “Low-complexity hybrid form FIR filters using matrix multiple constant multiplication,” in Proc. 38 th Asimolar Conf. Signals, Systems and Computers, vol. 1, pp. 77–80, Nov. 2001.
- [22] A. Shahein, M. Becker, N. Lotze, and Y. Manoli, “Power aware combination of transposed-form and direct-form FIR polyphase decimators for sigma-delta ADCs,” in Proc. 52nd IEEE Int. Midwest Symp. Circuits and Syst. MWSCAS '09, pp. 607– 610, Aug. 2009.
- [23] K. Y. Khoo, Z. Yu, and Willson, A.N., Jr., “Design of optimal hybrid form FIR filter,” in Proc. IEEE Int. Symp. Circuits and Syst. ISCAS 2001, vol. 2, pp. 621–624, May. 2001.
- [24] M. Murozuka, K. Ikeura, F. Adachi, K. Machida, and T. Waho, “Time- interleaved polyphase decimation filter using signed-digit adders”, 39th Int. Symp. Multiple-Valued Logic, pp. 245–249, May. 2009.
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