Early Power Estimation of Mixed-Signal Design

• Autorzy: Kotynia Ł. , Sathyamurthy M. , Neumann F. , Hennig E.
• Języki publikacji: EN

Abstrakty

EN

In this paper, we present the idea of using dynamic power estimation during the system-level design. A mixed-signal wireless IC with energy harvesting is used as an example of a device where power exploration and optimization plays a key role during the architecture planning. The novelty of this approach lies in introducing the activity profile for the mixed-signal chip as an important indicator of the power consumption that can drive the design phase. The method presented in this paper is based on modeling of the complete chip in order to apply it with a mixed-language Universal Verification Methodology (UVM) environment. It was decided to use the Verilog-D, SystemVerilog and Verilog-AMS languages to represent behavior of the digital and analog/mixed-signal parts of the chip.

Słowa kluczowe

EN

power profiling; Universal Verification Methodology; mixed-signal design

PL

Universal Verification Methodology; sygnał mieszany

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2012
• Tom: Vol. 3, nr 4
• Strony: 138--145
• Opis fizyczny: Bibliogr. 14 poz.

Twórcy

autor

Kotynia Ł.

autor

Sathyamurthy M.

autor

Neumann F.

autor

Hennig E.

• Department of Microelectronics and Computer Science, Lodz University of Technology, 90-924 Łódź,

Bibliografia

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• [5] D. Liu and C. Svensson, “Power Consumption Estimation in CMOS VLSI Chips,” IEEE Journal of Solid-State Ciruicts (1994), Vol.: 29 , Issue: 6, pp. 663-670
• [6] M. Nemani and F. Najm, "Towards a High-Level Power Estimation Capability", IEEE Trans. on CAD of Integrated Circuits and Systems 15 (1996), Vol. 15, Issue: 6, pp. 588-598, 1996
• [7] A Practical Guide to Low-Power Design. http://www.powerforward.org/DesignGuide.aspx/
• [8] Si2 Common Power Format Specification™. Version 2.0, Silicon Integration Initiative, Inc. (Si2TM)
• [9] Unified Power Format (UPF) Standard. Version 1.0, February 22, 2007
• [10] W. Hartong and S. Cranston, “Real Valued Modeling for Mixed Signal Simulation” January 2009
• [11] Y. Yun, J. Kim, N. Kim and B. Min, “Beyond UVM for Practical SoC Verification,” SoC Design Conference IS OCC (2011), pp. 158-162
• [12] N. Khan, Y. Kashai and H. Fang, “Metric Diven Verification of Mixed- Signal Designs,” Design and Verification Conference DVCon (2011).
• [13] J. M. Rabaey, A. Chandrakasan and B. Nikolic, “Digital Integrated Circuits (2nd Edition)”, Prentice Hall; 2nd edition (2003)
• [14] IEEE Standard Verilog® Hardware Description Language, The Institute of Electrical and Electronics Engineers, Inc., 2001