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Analysis and Design of a First - Order Delta-Sigma Modulator based on Ultra Incomplete Settling and Considering Non-ideal Effects

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One of the main building blocks of a Delta-Sigma modulator (ΔΣ?) is the integrator circuit. Usually this is implemented either in discrete or in continuous time domains using amplifiers. This paper analyses a ΔΣcircuit based on the implementation of passive switched-capacitor (SC) integrator using ultra incomplete settling. The behavior of a 1st order ΔΣ? is fully analyzed and explained, as well as its non-ideal effects, which become more significant for higher clock frequencies. This work compares performance of ΔΣM clocked with Fclk=100 MHz and Fclk=300 MHz. Electrical simulations show that the ΔΣM (Fclk=300 MHz) achieves a peak signal-to-noise-plus-distortion ratio (SNDR) of 67.5 dB, a peak signal-to-noise ratio (SNR) of 69.7 dB for a signal with a bandwidth (BW) of 400 kHz, while dissipating only 232μW from a 1.1 V power supply voltage, resulting in a figure-of-merit (FOM) of 165 fJ/conv.-step (simulated).
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  • Centre for Technologies and Systems (UNINOVA/CTS) and Departamento de Engenharia Electrotecnica, Faculdade de Ciencias e-Tecnologia, Universidade Nova de Lisboa (UNL), Campus FCT/UNL, 2829-516 Caparica, Portugal, b.nowacki@campus.fct.unl.pt
Bibliografia
  • [1] R. Schreier, J. Silva, J. Steensgaard, and G. C. Temes, “Design-oriented estimation of thermal noise in switched-capacitor circuits,” IEEE Trans. Circuits Syst .-I, vol. 52, no. 11, pp. 2358–2367, Nov. 2005.
  • [2] F. Chen and B. Leung, “A 0.25-mW low-pass passive sigma–delta modulator with built-in mixer for a 10-MHz IF input ,” IEEE J. Solid- State Circuits , vol. 32, pp. 774–781, Jun. 1997.
  • [3] F. Chen; Ramaswamy, S.; Bakkaloglu, B.; "A 1.5V 1mA 80dB passive Sigma-Delta ADC in 0.13 ? m digital CMOS process," Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International , vol., no., pp. 54- 477 vol.1, 2003.
  • [4] Yousry, R.; Hegazi, E.; Ragai, H.F.;"A Third-Order 9-Bit 10-MHz CMOS Sigma-Delta Modulator With One Active Stage," IEEE Trans. on Circuits and Systems I: Regular Papers , vol.55, no.9, pp.2469-2482, Oct. 2008.
  • [5] B. Nowacki, N. Paulino, J. Goes “A Second-Order Switched-Capacitor Sigma-Delta Modulator Using Very Incomplete Settling” IEEE International Symposium on Circuits and Systems, ISCAS’2011, May 2011
  • [6] Nyquist H., “Thermal agitation of electric charge in conductors”, Physical Review 1928;32:110–3.
  • [7] Oliveira, J.P.; Goes, J.; Esperanca, B.; Paulino, N.; Fernandes, J.; , "Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCs," IEEE International Symposium on Circuits and Systems, ISCAS’2007, , pp.3602-3605, May 2007.
  • [8] Kobayashi, T.; Nogami, K.; Shirotori, T.; Fujimoto, Y., "A current- controlled latch sense amplifier and a static power-saving input buffer for low-power architecture," Journal of Solid-State Circuits, IEEE , vol.28, no.4, pp.523-527, Apr 199
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bwmeta1.element.baztech-article-LODD-0002-0037
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