A 65 nm CMOS Resistorless Current Reference Source with Low Sensitivity to PVT Variations

• Autorzy: Łukaszewicz M. , Borejko T. , Pleskacz W. A.
• Języki publikacji: EN

Abstrakty

EN

This paper describes a resistorless current reference source, e.g. for fast communication interfaces. Addition of currents with opposite temperature coefficient (PTC and NTC) and body effect have been used to temperature compensation. Cascode structures have been used to improve the power supply rejection ratio. The reference current source has been designed in a GLOBALFOUNDRIES 65 nm technology. The presented circuit achieves 59 ppm/°C temperature coefficient over range of -40°C to 125°C. Reference current susceptibility to process parameters variation is ± 2.88%. The power supply rejection ratio without any filtering capacitor at 100 Hz and 10 MHz is lower than -142 dB and -131 dB, respectively.

Słowa kluczowe

EN

current reference; 65 nm CMOS; body effect; power supply circuits; threshold voltage

PL

efekt objętościowy; obwody zasilające; napięcie progowe

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2012
• Tom: Vol. 3, nr 4
• Strony: 119--124
• Opis fizyczny: Bibliogr. 7 poz.

Twórcy

autor

Łukaszewicz M.

autor

Borejko T.

autor

Pleskacz W. A.

• Institute of Microelectronics & Optoelectronics, Warsaw University of Technology, ul. Koszykowa 75, 00-662 Warszawa,

Bibliografia

• [1] W. Liu, W. Khalil, M. Ismail, E. Kussener, “A Resistor-Free Temperature Compensated CMOS Current Reference,” Proc. 2010 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 845, May 30 2010-June 2 2010.
• [2] K. Ueno, T. Hirose, T. Asai, Y. Amemiya, “A 1 W 600-ppm/ C Current Reference Circuit Consisting of Subtreshold CMOS Circuits,” IEEE Transaction on Circuits and Systems-II: Express Briefs, Vol. 57, No. 9.Spetember 2010.
• [3] W. Yi, H. Lenain, Y. Xiaolang, “All CMOS Temperature, Supply Voltage and Process Independent Current Reference,” 7th International Conference on ASIC, pp. 600, 22-25 October 2007.
• [4] C. Yoo, J. Park, “CM OS Current Reference with Supply and Temperature Compensation,” Electronics Letters 6th December 2007 Vol. 43 No. 25.
• [5] A. Bendali, Y. Audet, “A 1-V CMOS Current Reference with Temperature and Process Compensation,” IEEE Transaction on Circuits and Systems-I: Regular Papers, Vol. 54, No. 7, July 2007 .
• [6] I. M. Filanovsky, L. Najafizadeh, “Zeroing in On a Zero -Temperature Coefficient Point,” The 2002 45th Midwest Symposium on Circuits and Systems, 4-7 August 2002.
• [7] M. Łukaszewicz, T. Borejko, W. A. Pleskacz, “A Resistoreless Current Reference Source for 65 nm CMOS Technology with Low Sensitivity to Process, Supply Voltage and Temperature Variations,” Proceedings of the 2011 IEEE Symposium on Design and Diagnostic of Electronic Circuits and Systems – IEEE DDECS 2011, pp. 75-79, Cottbus, Germany, April 2011.