On-chip Parametric Test of R-2R Ladder Digital-to-Analog Converter and Its Efficiency

• Autorzy: Arbet D. , Stopjakova V. , Brenkus J. , Gyepes G.
• Języki publikacji: EN

Abstrakty

EN

This paper deals with the investigation of the fault detection in separated parts of a mixed-signal integrated circuit example by implementing parametric test methods. The experimental Circuit Under Test (CUT) consisting of an 8-bit binary-weighted R-2R ladder digital-to-analog converter and additional on-chip test hardware was designed in a standard 0.35 μm CMOS technology. For detection of catastrophic and parametric faults considered in different parts of the CUT, two dedicated parametric test methods: oscillation-based test technique and IDDQ monitoring were used. For the operational amplifier, on-chip and off-chip approaches have been used to compare the efficiency of both approaches in covering catastrophic faults that are hard to detect. For respective converter parts, the excellent fault coverage of 94.21% of hard-detectable faults by the proposed parametric tests was achieved.

Słowa kluczowe

EN

fault detection; catastrophic faults; parametric faults; on-chip parametric test; mixed-signal test

PL

wykrywanie uszkodzeń; uszkodzenie katastroficzne; uszkodzenia parametryczne; test parametryczny; mieszany test sygnału

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2012
• Tom: Vol. 3, nr 2
• Strony: 73--80
• Opis fizyczny: Bibliogr. 27 poz.

Twórcy

autor

Arbet D.

autor

Stopjakova V.

autor

Brenkus J.

autor

Gyepes G.

• Institute of Electronics and Photonics, Faculty of Electrical Engineering and Information Technology, Slovak University of Technology, Ilkovicova 3, Bratislava 812 19, Slovakia,

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