Analog Circuits Sizing Using the Fixed Point Iteration Algorithm with Transistor Compact Models

• Autorzy: Javid F. , Iskander R. , Durbin F. , Louerat M.-M.
• Języki publikacji: EN

Abstrakty

EN

This paper presents an algorithm, based on the fixed point iteration, to solve for sizes and biases using transistor compact models such as BSIM3v3, BSIM4, PSP and EKV. The proposed algorithm simplifies the implementation of sizing and biasing operators. Sizing and biasing operators were originally proposed in the hierarchical sizing and biasing methodology [1]. They allow to compute transistors sizes and biases based on transistor compact models, while respecting the designer's hypotheses. Computed sizes and biases are accurate, and guarantee the correct electrical behavior as expected by the designer. Sizing and biasing operators interface with a Spice-like simulator, allowing possible use of all available compact models for circuit sizing and biasing over different technologies. A bipartite graph , that contains sizing and biasing operators, is associated to the design view of a circuit, it is the design procedure for the given circuit. To illustrate the effectiveness of the proposed fixed point algorithm, a folded cascode OTA is efficiently sized with a 130nm process, then migrated to a 65nm technology. Both sizing and migration are performed in a few milliseconds.

Słowa kluczowe

EN

analog IP; analog sizing; design reuse; bipartite graphs; transistor compact models; technology migration

PL

IP analogowe; graf dwudzielny; model tranzystora; migracja technologii

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2012
• Tom: Vol. 3, nr 1
• Strony: 7--14
• Opis fizyczny: Bibliogr. 22 poz.

Twórcy

autor

Javid F.

autor

Iskander R.

autor

Durbin F.

autor

Louerat M.-M.

• LIP6 Laboratory, University Pierre and Marie Curie, Paris, France,

Bibliografia

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