Projektowanie analogowych układów scalonych CMOS o strukturze sieci neuronowej do przetwarzania obrazów i sygnałów

Kowalski, J.

Artykuł - szczegóły

Tytuł artykułu

Projektowanie analogowych układów scalonych CMOS o strukturze sieci neuronowej do przetwarzania obrazów i sygnałów

Autorzy

Kowalski J.

Identyfikatory

Warianty tytułu

Designing CMOS analog integrated circuits to implement neural networks for image and signal processing

Języki publikacji

Abstrakty

W monografii przedstawiono wyniki prac autora dotyczące projektowania i testowania prototypowych, analogowych układów scalonych CMOS, odpowiednich do neuronowego przetwarzania obrazów i sygnałów, na przykładzie trzech zaprojektowanych i przetestowanych układów scalonych. Układy zostały wykonane przez konsorcjum Europractice w różnych technologiach CMOS, tj. 2,4 μm, 0,8 μm oraz 0,35 μm W zaprojektowanych układach oprócz właściwej sieci neuronowej implementowano specjalne struktury testowe, które umożliwiły wykonanie pomiarów podstawowych bloków funkcjonalnych sieci. Pozwoliło to na porównanie wyników symulacji z pomiarami oraz na uzyskanie informacji wykorzystanych do budowy stanowiska do testowania poprawności działania wykonanych układów scalonych. Dla każdego układu zaprojektowano specjalne stanowisko pomiarowe, które umożliwiło weryfikację doświadczalną działania danej sieci neuronowej. Pierwszym prezentowanym układem scalonym jest sieć Kohonena, dedykowana do zadań identyfikacji parametrów układów dynamicznych, przetwarzająca dane w sposób analogowy. Przedstawiono architekturę układu realizującego sieć, jego implementację w technologii MIETEC 2,4 μm oraz wyniki pomiarów podstawowych bloków funkcjonalnych sieci. Drugim zaprezentowanym układem scalonym jest filtr ważonych statystyk porządkowych obrazu o architekturze sieci neuronowej komórkowej, zaprojektowany w technologii AMS 0,8 μm CYE. Omówiono model komórki tego filtru oraz jego architekturę. Podano też szczegółowy opis bloków funkcjonalnych wchodzących w skład filtru oraz wyniki badań eksperymentalnych. Ostatnią część monografii stanowi projekt sieci neuronowej zbudowanej z synchronizowanych oscylatorów, służącej do segmentacji obrazów binarnych. W pracy zaproponowano nowy model oscylatora oraz architekturę układu scalonego realizującego sieć. Przedstawiono również projekt układu scalonego wykonanego w technologii AMIS 0,35 μm C035M-D 5M/1P i wyniki pomiarów.

This monograph summarizes Author's research in the field of designing and testing CMOS prototype analog-integrated-circuit neural networks for image and signal processing. Three chips are presented which implement three various types of neural networks. The circuits have been designed using different CMOS technologies offered by Europractice, i.e. 2,4 μm, 0,8 μm and 0,35 μm ones. Apart from a main neural network, special test structures have been implemented in the circuits. The test structures enable the neural-network basic building blocks to be measured. This allows us to compare simulation with measurement results and provides some information needed for proper designing the integrated-circuit functional-test set-up. A special test set-up has been realized for each integrated circuit to perform functional verification of a given neural network. The first ASIC circuit considered in this monograph is a Kohonen network, operating with analog signals, dedicated for estimation of dynamic-system parameters. Architecture of the circuit, its implementation in the MIETEC 2,4 μm technology, as well as measurement results has been presented. The second integrated circuit presented in the monograph is a filter, based on a cellular neural network architecture, suitable for weighted-order-statistic image processing. It has been designed in the AMS 0,8 μm CYE technology. The filter cell model and structure have been described. Detailed description of its basic building blocks and the chip test results have been shown. The final part of this monograph is a description of a synchronized-oscillators-based neural network implemented in an ASIC form, which is well suited for binary-image-segmentation tasks. A new oscillator model and architecture of the designed circuit have been proposed. The AMIS 0,35 μm C035M-D 5M/1P technology has been used. Design, simulation and measurement results have been presented as well.

Słowa kluczowe

sieci neuronowe układ scalony CMS przetwarzanie obrazów przetwarzanie sygnałów analogowe układy CMOS sieć Kohonena filtr ważonych statystyk porządkowych sieć synchronizowanych oscylatorów

neural networks CMOS integrated circuits image processing signal processing analog CMOS Kohonen network weighted order statistic filter network of synchronised oscillators

Wydawca

Wydawnictwo Politechniki Łódzkiej

Czasopismo

Zeszyty Naukowe. Rozprawy Naukowe / Politechnika Łódzka

Rocznik

2012

Tom

Z. 420

Strony

1--135

Opis fizyczny

Bibliogr. 165 poz.

Twórcy

autor

Kowalski J.

Instytut Elektroniki Politechniki Łódzkiej

Bibliografia

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