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Modeling the characteristics of high-k HfO2-Ta2O5 capacitor in Verilog-A

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A circuit simulation model of a MOS capacitor with high-k HfO2-Ta2O5 mixed layer is developed and coded in Verilog-A hardware description language. Model equations are based on the BSIM3v3 model core. Capacitance-voltage (C-V) and current-voltage (I-V) characteristics are simulated in Spectre circuit simulator within Cadence CAD system and validated against experimental measurements of the HfO2-Ta2O5 slack structure.
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Bibliografia
  • [1] G. Angelov, T. Takov, and St. Ristic "MOSF'ET Models al the Edge of 100-nm Sizes", in Proc. 24th Intl. Conf. on Microelectronics (MIEL 2004), NiS, Serbia and Montenegro, 2004, vol. 1, pp. 295-298.
  • [2] S. Deleonibus, Electronic Device Architectures far the Nano-CMOS Era From Ultimate CMOS Scaling to Beyond CMOS Devices, Pan Stanford Publishing Pie., Singapore, 2009.
  • [3] K. J. Kuhn, "CMOS scaling beyond 32nm: Challenges and opportunities", in Proc. 46th ACM/IEEE Design Automation Conf. (DAC 2019), San Francisco, CA, 2009, pp. 310-313.
  • [4] The International Technology Roadrnap for Semiconductors - 2009 Edition [Online]. Available: http://www.itrs net/Links/2009ITRS/Home2009.htm
  • [5] R. Chau et al. "Application of High-k Dielectrics and Metal Gate Electrodes to Enable Silicon and Non-Silicon Logic Nanotechnology", Microelectronic Engineering, 2005, vol. 80, pp. 1 -6.
  • [6] G. D Wilk, R. M.Wallace, and J. M. Anthony, "High-k Gale Dielectrics: Current Status and Materials Properties Considerations," J. Appl Phys., 2001, vol. 89, pp. 5243-5275.
  • [7] M. Houssa, ed., "Hjgh-k Gate Dielectrics", Institute of Physics Publishing. Bristol and Philadelphia, 20W ISBN 0-7503-0906-7.
  • [8] E. Atanassova and A. Paskaleva, "Challenges of TaO5 as high-k dielectric for nanoscale DRAMs", Microelectronics Reliability 47(6), 2007, pp. 913-923.
  • [9] M. Mierzwinski, P. O'Halloran, B. Troyanovsky, R. Dutton, "Changing the paradigm for compact model integration in circuit simulators using Verilog-A", Technical Proc. 2001 Nanotechnology Conf. anil Trade Show (Nanotech 2003), February 2003, vol. 2, pp. 376-379.
  • [10] E. Atanassova, M. Georgieva, D. Spassov, and A. Paskaleva, "High-k HfO2-Ta2O5 mixed layers: Electrical characteristics and mechanisms of conductivity", Microel. Engin. 87, 2010, pp. 668-676.
  • [11] K. J. Yang, C. Hg, "MOS Capacitance Measurements for High-Leakage Thin Dielectrics", IEEE Transactions on Electron Devices, Vol. 46, No. 7, July 1999.
  • [12] C-Y Characterization of MOS Capacitors Using the Model 4200-SCS Semiconductor Characterization System, KEITHLEY Application Note Series, No. 2896.
  • [13] Y. Checng, et. al. "BSIM3v3.1 User's Mannar, Memorandum No. UCB/ERL M97/2, 1997.
  • [14] E. H. NicollianandJ. R. Brews, "MOS (Mala! (hide Semiconductor; Physics and Technology", Wiley-Interscience, New York, 1982.
  • [15] Cadence Design Systems, Inc., Staff, "Cadence Circuit Components and Device Models Manual", Product Version 6.0 Spectre, Cadence Design Systems, Inc. 11/2005.
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Bibliografia
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bwmeta1.element.baztech-article-LOD7-0029-0064
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