Automated substrate resistance extraction in nanoscale VLSI by exploiting a geometry-based analytical model

• Autorzy: Bontzios Y. I. , Dimopoulos M. G. , Hatzopoulos A. A.
• Języki publikacji: EN

Abstrakty

EN

In this work, a new automated method for determining the substrate resistance is presented. It exploits a geometric formulation of the current streamlines between coupled structures and builds an analytical model for the substrate resistance. Both simulation and measurement data are utilized in order to show the validity of the proposed scheme. The measurement data are obtained from a fabricated test chip. The results show that the proposed method succeeds in computing the substrate resistance while the average error falls within 5%.

Słowa kluczowe

EN

substrate noise; integrated circuits; geometric modeling; resistance extraction; resistance modeling; parasitics

PL

szum podłożowy; układ scalony; modelowanie geometryczne; pochodzenie oporu; modelowanie oporu; zasilanie pasożytnicze

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2011
• Tom: Vol. 2, nr 3
• Strony: 81--87
• Opis fizyczny: Bibliogr. 17 poz.

Twórcy

autor

Bontzios Y. I.

autor

Dimopoulos M. G.

autor

Hatzopoulos A. A.

Bibliografia

• [1] Wu J. H., and J. A. del Alamo, "Fabrication and Characterization of Through-Substrate Interconnects", IEEE Transactions on Electron Devices, vol 57.no. 6, pp. 1261-1268, 2010.
• [2] Y. Yuan and P Banerjee, "ICE: Incremental 3-Dimensional Capacitance and Resistance Extraction for an Iterative Design Environment", Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 64-67, Mar. 1999.
• [3] E. Salman, R. Jakushokas, E. G. Fncdman, R. M. Secarcanu, and O. L. Hartin. "Contact Merging Algorithm for Efficient Substrate Noise Analysis in Large Scale Circuits", Proceedings of the ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI), pp. 9-14, May 2009.
• [4] E. Schrik and N. P. van dcr Meijs, "Combined BEM/FEM Substrate Resistance Modeling," Proceedings of the IEEE/ACM Design Automation Conference, pp. 771-776, June 2002.
• [5] Y. Bontzios, A. Hatzopoulos, "A Unified Method for Calculating Capacitivc and Resistive Coupling Exploiting Geometry Constraints on Lightly and Heavily Doped CMOS Processes", IEEE Transactions on Electron Devices, Vol. 57, Iss. 8, pp. 1751-1760, Aug. 2010.
• [6] P. Eyben, D. Alvarez, M. Jurczak, R. Rooyackers, A. De Keersgieter, E. Augendre, and W. Vandervorst, "Analysis of the two-dimcnsional-dopant profile in a 90 nm complementary metal-oxide-semiconductor technology using scanning spreading resistance microscopy". Journal of Vacuum Science & Technology, vol. 21, no. 1, pp. 364-368, 2004.
• [7] P. Eyben, M. Xu, N. Duhayon, T. Clarysse, S. Callewaert, and W. Vandervorst, "Scanning spreading resistance microscopy and spectroscopy for routine and quantitative two-dimensional carrier profiling", Journal of Vacuum Science & Technology, vol. 20, no 1, pp. 471-178, 2002.
• [8] S. Morita, "Roadmap of Scanning Probe Microscopy (NanoScience and Technology)", Springer, Nov 2006, pp. 18.
• [9] S. Bronckers, K. Scheir, G.V. Plas, G. Vandersteen, Y. Rolam, "A Methodology to Predict the Impact of Substrate Noise in Analog/RF Systems", IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol.28 no.l1, p.1613-1626, Nov. 2009.
• [10] Ajit Sharma, Patrick Birrer, Sasi Kumar Arunachalam , Chcnggang Xu, Tern S. Fiez, Kartikeya Mayaram, "Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, v.13 n.7, p.843-851, Jul. 2005.
• [11] Peterson, B.; Mayaram, K.; Ficz, T.S., "Automated Extraction of Model Parameters for Noise Coupling Analysis in Silicon Substrates", IEEE Custom Integrated Circuits Conference, 2007. C1CC '07, pp. 853-856, Sept. 2007.
• [12] Andrew F. Peterson, "Computational Methods for Electromagnetics", Wiley-Blackwell: 1997, pp. 24-34.
• [13] B. Charbon et a!., "Substrate Noise Analysis and Optimization for IC Design, Springer, Apr. 2001.
• [14] Comsol, Fernlab 3.l. [Online]. Available: http:/www.comsol.com
• [15] Cascade Microtcch, Inc. [Online], Available; http://www.cmicro.com.
• [16] Hameg Instruments, [Online], Available: hrtp: //www. electronics.norm.gr/dmm/dmm.html.
• [17] American Probe & Technologies, Inc., [Online], Available: http://www.amcricanprobe. com/72t.htm.