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Rapid prototyping of recursive hardware: Karatsuba-Ofman's multiplication algorithm

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Języki publikacji
EN
Abstrakty
EN
It is a fairly hard task TO design hardware that implements recursive computations using a repetitive style, which is supported in mast hardware description languages suck as VHDL and Verilog. In this paper we show how one can very elegant and rapidly yield hardware models that implement recursive computations. The hardware model is expressed in the most popular hardware description language VHDL As a case study, we implement the Karatsuba-Ofman's divide-and-conquer multiplication algorithm. The generated hardware is efficient in terms of response time and compact in terms of hardware area.
Rocznik
Strony
43--59
Opis fizyczny
Bibliogr. 14 poz.
Twórcy
autor
  • Departament of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil
  • Departament of Systems Engineering and Computation, Faculty of Engineering, State University of Rio de Janeiro, Rio de Janeiro, Brazil
Bibliografia
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  • [6] Knuth D.E.: The art of computer programming: seminumerical algorithms, vol 2, 2nd Edition, Addison-Wesley, Reading, Mass., 1981.
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  • [8] Dhem J.F.: Design of an efficient public-key cryptographic library for RISC-based smart cards, Ph.D. Thesis, Faculty of Applied Science, Catholic University of Louvain, May 1998.
  • [9] Jung M., Madlener F., Ernst M. and Huss S.A.: A reconfigurable coprocessor for finite field multiplication in GF(2n), Proc. of IEEE Workshop on Heterogeneous Reconfigurable systems on Chip, Hamburg, Germany, 2002.
  • [10] Paar C.: A new architecture for a parallel finite field multiplier with low complexity based on composite fields, IEEE Transactions on Computers, vol. 45, no. 7, pp. 856-861, 1996.
  • [11] Navabi Z.: VHDL - analysis and modelling of digital systems, 2nd Edition, MacGrawHill, 1998.
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  • [13] Xilinx, Inc. Foundation Series Software, http://www.xilinx.com.
  • [14] Kim J.H., Ryu J. H.: A high speed and low power VLSI multiplier using a redundant binary Booth encoding, Proc. of 6th Korean Semiconductor Conference, PA-30. 1999
Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-LOD7-0027-0071
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