Digitally programmable delay-locked-loop with variable charge pump current

• Autorzy: Lopes B. , Paulino N. , Goes J. , Steiger-Garçăo A.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a digitally programmable delay line intended for use as timing generator in a RADAR ranging system. The architecture of the programmable delay uses a ΣΔ modulator to generate a reference clock with a delay unaffected by component matching. This reference clock has a large jitter noise component that is filtered by delay lock loop (DLL). The programmable delay can produce a delay ranging from 20 ns to 100 ns, because of the large delay variation, it is necessary to use a variable charge pump current in the DDL, in order to guaranty stability for all the desired delay values. The electrical design of the circuit, in a 0.13-/žm 1.2-V CMOS technology, will be presented, as well as electrical simulations results of the complete system.

Słowa kluczowe

EN

delay-locked loop; digitally programmable delay; ultra wideband

PL

opóźnienie locked-loop; cyfrowo programowalne opóźnienie; ultra szerokie pasmo

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 3
• Strony: 269--276
• Opis fizyczny: Bibliogr. 8 poz.

Twórcy

autor

Lopes B.

autor

Paulino N.

autor

Goes J.

autor

Steiger-Garçăo A.

• Department of Electrical Engineering, Faculdade de Ciencias e Tecnologia, and with the Center of Technology and Systems (CTS-UNINOVA). Universidade Nova de Lisboa, 2829-516 Caparica, Portugal,

Bibliografia

• [1] McEwan. "Ultra-Wideband Receiver", US Patent 5523760, June 1996.
• [2] Low Power UWB CMOS Radar Sensors; Nuno Paulino, Joao Goes, Adolfo Steiger Garçao, Springer, ISBN 978-1-4020-8409-6.
• [3] N. Paulino, M. Serrazina, J. Goes and A. Steiger-Garcao, "Design of a Digitally Programmable Delay-Locked-Loop for a Low-Cost Ultra Wide Band Receiver", Circuits and Systems, 2003. 1SCAS '03.
• [4] RF Microelectronics; Behzad Razavi. Prentice Hall, ISBN 0-13-887571-5.
• [5] W. Rhee, "Design of High-Performance CMOS Charge Pumps in Phase-Locked Loops," IEEE Int. Symp. Circuits and Systems, Vol. 1, pp. 545-548, 1999.
• [6] M. Soyuer, J. F. Ewen, and H. L. Chuang, "A Fully Monolithic 1.25 GHz CMOS Frequency Synthesizer". Symp. VLSI Circuits Dig. Tech. Papers, pp. 127-128. June 1994.
• [7] B. Razavi, "Monolithic Phase-Locked Loops and Clock Recovery Circuits", pp.1-39, IEEE Press, 1996.
• [8] J. Maneatis, "Low-Jitter and Process-Independent DLL and PLL Based on Self-Biased Techniques". ISSCC Digest of Technical Papers, 1996.