A solution to low power switched capacitor integrator design with reduced effective input capacitance

• Autorzy: Korkmaz S. , Dundar G.
• Języki publikacji: EN

Abstrakty

EN

A novel low power Switched Capacitor Integrator with reduced effective input capacitance is proposed in this paper. It is mainly based on reducing the effective input sampling capacitance by charge sharing with an extra capacitance, such that the integration capacitance can be chosen much smaller while maintaining the same sampling to integration capacitance ratio. Reducing the integration capacitance will result in less integration current and less integration current will in turn result in less power over the integrator which is the main goal of this work, reducing the integrator power consumption and chip area. Another main advantage of this configuration is, that it can be used in large time constant integrators without using physically large integration capacitance.

Słowa kluczowe

EN

low power integrator; very large time constant integrator; effective capacitance reduction; switched capacitor integrator

PL

integrator małej mocy; bardzo duża stała czasowa integratora; skuteczne zmniejszenie pojemności; włączony integrator kondensatora

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 3
• Strony: 229--235
• Opis fizyczny: Bibliogr. 11

Twórcy

autor

Korkmaz S.

autor

Dundar G.

• Electrical and Electronics Engineering Department, Bogazici University, Istanbul 34342, Turkey,

Bibliografia

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• [8] K. I. N.A. Radev, "Area-efficient gain- and offset-compensated very-large-time-constant sc integrator," March 2000, pp. 394-396.
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