Fault modeling and analysis of short defects in CMOS based reversible circuits

• Autorzy: Amaricai A. , Boncalo O.
• Języki publikacji: EN

Abstrakty

EN

This paper presents a SPICE based analysis of reversible circuits affected by the short defects: the gate oxide defect and the source-drain defect. The simulations are performed using realistic transistor models (the BSIM4 model) and take into account the resistive nature of the gate oxide and the source drain shorts. We aim at determining dependence between the short's resistance and the output voltage. Furthermore, we analyze the timing characteristics of reversible circuits affected by such faults. The goal is to develop logic and delay fault models for CMOS based reversible gates. This way, Boolean test strategies and logic level fault tolerant mechanisms and strategies can be devised for reversible circuits.

Słowa kluczowe

EN

reversible circuits; fault modeling; testing; short

PL

odwracalne obwody; modelowanie błędów; testowanie; zwarcie

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 2
• Strony: 175--179
• Opis fizyczny: Bibliogr. 21 poz.

Twórcy

autor

Amaricai A.

autor

Boncalo O.

• Universita Politehnica of Timisoara, Faculty of Automation and Computer Engineering,

Bibliografia

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