Distributed approach for parallel exact critical path tracing fault simulation

• Autorzy: Ivask E. , Devadze S. , Ubar R.
• Języki publikacji: EN

Abstrakty

EN

Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Fault simulation used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up simulation and to overcome the problem of memory limits in the case of very large circuits, a method of model partitioning and the procedure of parallel reasoning for several distributed simulation agents was proposed. The concept and implementation of web-based distributed system was introduced.

Słowa kluczowe

EN

distributed computing; fault simulation; critical path tracing; digital test

PL

systemy rozproszone; symulacja błędów; śledzenie ścieżki krytycznej; cyfrowy test

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 2
• Strony: 165--174
• Opis fizyczny: Bibliogr. 36 poz.

Twórcy

autor

Ivask E.

autor

Devadze S.

autor

Ubar R.

• Department of Computer Engineering Tallinn University of Technology Tallinn, Estonia,

Bibliografia

• [1] Han and Soo-Young Lee, "A Parallel Implementation of Fault Simulation on a Cluster of Workstations," in Proc. IEEE International Symposium Parallel and Distributed Processing IP DPS, 2008.
• [2] E. M. Rudnick and J. H. Patel, "Overcoming the serial logic simulation bottleneck in parallel fault simulation," in Proc 10th Int. Conf. VLSI Design, 1997, pp. 495-501.
• [3] R. B. Mueller-Thuns, D. G. Saab, R. F. Damiano, and J. A. Abraham, "Portable parallel logic and fault simulation," in Proc. int. Conf CAD, 1989, pp. 506-509.
• [4] J. F. Nelson, "Deductive fault simulation on hypercube multiprocessors," in Proc. 9th ATT Conf. Electronic Testing, 1987.
• [5] S. Patil, P. Banerjee, and J. Patel, "Parallel test generation for sequential circuits on general purpose multiprocessors," in Proc. 28th ACM/IEEE Design Automation Conf., San Fransisco, CA, 1991.
• [6] S. Ghosh, "NODIFS: A noval, distributed circuit partitioning based algorithm for fault simulation of combinational and sequential digital designs on loosely coupled parallel processors," LEMS, Division of Engineering, Brown University, Providence, RI, Tech. Rep., 1991.
• [7] P. Agrawal and V. D Agrawal, K. T. Cheng, and R. Tutundjian, "Fault simulation in a pipelined multiprocessor system," in Proc. Int. Test Conf, 1989, pp. 727-734.
• [8] S. Bose and P. Agrawal, "Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers," in Proc. Design Automation Conf, 1992, pp. 332-335.
• [9] M. B Amin and B. Vinnakota, "Data Parallel-Fault Simulation," IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 183-190, Jun. 1999.
• [10] M. Abramovici, P.R. Menon and D.T. Miller, "Critical Path Tracing - an Alternative to Fault Simulation," in Proc. 20th Design Automation Conf, 1983,pp.214-220.
• [11] L. Wu and D M H Walker, "A Fast Algorithm for Critical Path Tracing in VLSI", in Proc. Int. Symp. Defect and Fault Tolerance in VLSI Sterns, 2005, pp. 178-186
• [12] S. Devadze, J. Raik, A Jutman and R. Ubar, "Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using SSBDDs", in Proc. 7th IEEE LATW Conf, 2006, pp.97-102.
• [13] R. Ubar, S. Devadze, J. Raik and A. Jutman, "Parallel Fault Backtracing for Calculation of Fault Coverage", in Ptoc. 13th Asia and South Pacific Design Automation Conference (ASPDAC), Korea, 2008, pp. 667-672.
• [14] J. Raik and R. Uhar, "Feasibility of Structurally Synthesized BDD Models for Test Generation," in Proc. European Test Workshop, Barcelona, 1998, pp. 145-146.
• [15] S. Devadze, R. Ubar, J. Raik and A. Jutman, "Parallel Exact Critical Path Tracing Fault Simulation with Reduced Memory Requirements," in Proc. 4th IEEE Int Conf. Design & Technology of Integrated Systems in Nanoscale Era, Cairo, Egypt, 2009.
• [16] A. Schneider et. al. "Internet-based Collaborative Test Generation with MOSCITO," in Proc. DATE, Paris, France, 2002, pp 221-226.
• [17] E Ivask, J. Raik, R. Ubar and A. Schneider, "WEB-Based Environment. Remote Use of Digital Electronics Test Tools," in Virtual Enterprises and Collaborative Networks, Kluwer Academic Publishers, 2004, pp. 435-442
• [18] BOINC. http //boinc.berkeley.edu/
• [19] Y.M. Teo and X. B. Wang, "AliCE: A Scalable Runtime Infrastructure for High Performance Grid Computing," in Proc. IFIP Int. Conf. Network and Parallel Computing, Springer-Verlag Lecture notes in Computer Science, Wuhan, China, October 2004.
• [20] K. Gulati, S. P. Khatri, "Towards Acceleration of Fault Simulation using Graphics Processing Units," in Proc. DAC, Anaheim, California, 2008.
• [21] C. Bauer and G. King ,Hibernate in Action. Manning Publications, 2004
• [22] C. Walls, Spring in Action, Third Edition. Manning Publications, 2011.
• [23] D. Panda, R Rahman and D. Lane, EJB 3 in Action. Manning Publications, First Edition, 2007.
• [24] Java Servlet Technology. http.//Java.sun com/products/servlel/overview, html
• [25] Open source database MySQL. http://www.mysql.com/why-mysql/
• [26] Apache Tomcat, http //tomcat.apache.org/
• [27] NetBeans IDE. http://netbeans org/features/
• [28] Ian Foster "Globus Toolkit Version 4: Software for Service-Oriented Systems", Journal of Computer Science and Technology,vol. 21, no.4, pp. 513-520, Jul, 2006.
• [29] D. Booth, H Haas, F. McCabe el. al., "Web Services Architecture," W3C Working Group Note, 2004. http://www w3.org/TR/ws-arch/
• [30] TeraGrid. http://www.teragrid org/about/
• [31] Open Science Grid http://www.opensciencegrid.org/
• [32] Large Hadron Collider (LHC) Computing Grid http://public.web.cern.ch/public/en/lhc/Computing-en.html
• [33] Java Jini Technology, http://www.jini.org/wiki/
• [34] JavaSpaces. http://www.jini.org/wiki/JavaSpaces_Specification
• [35] Simple Object Access Protocol (SOAP), http://www.w3.org/TR/soap/
• [36] M. Abramovici, M.A.Breuer and A.D. Friedma, Digital systems testing and testable design. IEEE Press, 1990.