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Języki publikacji
Abstrakty
Distributed computing attempts to aggregate different computing resources available in enterprises and in the Internet for computation intensive applications in a transparent and scalable way. Fault simulation used in digital design flow for test quality evaluation can require a lot of processor and memory resources. To speed up simulation and to overcome the problem of memory limits in the case of very large circuits, a method of model partitioning and the procedure of parallel reasoning for several distributed simulation agents was proposed. The concept and implementation of web-based distributed system was introduced.
Rocznik
Tom
Strony
165--174
Opis fizyczny
Bibliogr. 36 poz.
Twórcy
autor
autor
autor
- Department of Computer Engineering Tallinn University of Technology Tallinn, Estonia, ieero@pld.ttu.ee
Bibliografia
- [1] Han and Soo-Young Lee, "A Parallel Implementation of Fault Simulation on a Cluster of Workstations," in Proc. IEEE International Symposium Parallel and Distributed Processing IP DPS, 2008.
- [2] E. M. Rudnick and J. H. Patel, "Overcoming the serial logic simulation bottleneck in parallel fault simulation," in Proc 10th Int. Conf. VLSI Design, 1997, pp. 495-501.
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- [5] S. Patil, P. Banerjee, and J. Patel, "Parallel test generation for sequential circuits on general purpose multiprocessors," in Proc. 28th ACM/IEEE Design Automation Conf., San Fransisco, CA, 1991.
- [6] S. Ghosh, "NODIFS: A noval, distributed circuit partitioning based algorithm for fault simulation of combinational and sequential digital designs on loosely coupled parallel processors," LEMS, Division of Engineering, Brown University, Providence, RI, Tech. Rep., 1991.
- [7] P. Agrawal and V. D Agrawal, K. T. Cheng, and R. Tutundjian, "Fault simulation in a pipelined multiprocessor system," in Proc. Int. Test Conf, 1989, pp. 727-734.
- [8] S. Bose and P. Agrawal, "Concurrent fault simulation of logic gates and memory blocks on message passing multicomputers," in Proc. Design Automation Conf, 1992, pp. 332-335.
- [9] M. B Amin and B. Vinnakota, "Data Parallel-Fault Simulation," IEEE Trans. VLSI Systems, vol. 7, no. 2, pp. 183-190, Jun. 1999.
- [10] M. Abramovici, P.R. Menon and D.T. Miller, "Critical Path Tracing - an Alternative to Fault Simulation," in Proc. 20th Design Automation Conf, 1983,pp.214-220.
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- [12] S. Devadze, J. Raik, A Jutman and R. Ubar, "Fault Simulation with Parallel Critical Path Tracing for Combinational Circuits Using SSBDDs", in Proc. 7th IEEE LATW Conf, 2006, pp.97-102.
- [13] R. Ubar, S. Devadze, J. Raik and A. Jutman, "Parallel Fault Backtracing for Calculation of Fault Coverage", in Ptoc. 13th Asia and South Pacific Design Automation Conference (ASPDAC), Korea, 2008, pp. 667-672.
- [14] J. Raik and R. Uhar, "Feasibility of Structurally Synthesized BDD Models for Test Generation," in Proc. European Test Workshop, Barcelona, 1998, pp. 145-146.
- [15] S. Devadze, R. Ubar, J. Raik and A. Jutman, "Parallel Exact Critical Path Tracing Fault Simulation with Reduced Memory Requirements," in Proc. 4th IEEE Int Conf. Design & Technology of Integrated Systems in Nanoscale Era, Cairo, Egypt, 2009.
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Typ dokumentu
Bibliografia
Identyfikator YADDA
bwmeta1.element.baztech-article-LOD6-0024-0009