Methodology for the digital calibration of analog circuits and systems using sub-binary radix DACs

• Autorzy: Pastre M. , Kayal M
• Języki publikacji: EN

Abstrakty

EN

This paper presents a methodology for digitally calibrating analog circuits and systems. Based on the detection of an imperfection by a simple comparator, a successive approximations algorithm tunes a compensation current. The latter is generated by a sub-binary radix M/2+M DAC, which has the advantage of allowing reaching arbitrarily high resolutions at the cost of extremely small area. The methodology proposed allows the removal of any type of imperfections, at the expense of two shift registers, a few logical gates and a DAC which is smaller than the shift register.

Słowa kluczowe

EN

calibration; sub-binary DACs; M/2+M; offset compensation; deep submicron; variability

PL

wzorcowanie; sub binarny DACs; przeniesienie kompensancji; głębokie sub mikrony; zmienność

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 1
• Strony: 25--30
• Opis fizyczny: Bibliogr. 10 poz.

Twórcy

autor

Pastre M.

autor

Kayal M

• E- Lab EPFL CH-1015 Lausanne, Switzerland

Bibliografia

• [1] M. Pastre, M. Kayal, H. Blanchard, "A Hall Sensor Analog Front End for Current Measurement with Continuous Gain Calibration", IEEE International Solid-State Circuits Conference (ISSCC), pp. 242-243, 596, February 2005
• [2] M. Pastre, M. Kayal, H. Blanchard, "A Hall Sensor Analog Front End for Current Measurement with Continuous Gain Calibration", IEEE Sensors Journal, Special Edition on Intelligent Sensors, Vol. 7, Number 5, pp. 860-867, May 2007
• [3] M. Kayal, M. Pastre, "Automatic Calibration of Hall Sensor Microsystems", Elsevier's Microelectronics Journal, Vol. 37, pp. 1569-1575, December 2006
• [4] P. Fazan, S. Okhonin, M. Nagoga, J. M. Sallese, L. Portmann, R. Ferrant, M. Kayal, M. Pastre, M. Blagojevic, A. Borschberg, M. Declercq, "Capacitor-Less 1-Transistor DRAM", IEEE International SOI Conference, pp. 10-13, October 20
• [5] M. Blagojevic, M. Pastre, M. Kayal, P. Fazan, S. Okhonin, M. Nagoga, M. Declercq, "SOI Capacitor-Less 1-Transistor DRAM Sensing Scheme with Automatic Reference Generation", IEEE Symposium on VLSI Circuits, pp. 182-183, June 2004
• [6] M. Blagojevic, M. Kayal, M. Pastre, L. Harik, S. Okhonin, P. Fazan, "Capacitor-Less IT DRAM Sensing Scheme with Automatic Reference Generation", IEEE Journal of Solid-State Circuits (JSSC), Vol. 41, pp. 1463-1470, June 2006
• [7] M. Kayal, R. T. L. Sáez, M. Declercq, "An automatic Offset Compensation Technique Applicable to Existing Operational Amplifier Core Cell", IEEE Custom Integrated Circuits Conference, pp 419-422, May 1998
• [8] M. Pastre, M. Kayal, "High-precision DAC based on a self-calibrated sub-binary radix converter", IEEE International Symposium on Circuits and Systems (ISCAS), Vol. 1, pp. 341-344, May 2004
• [9] K. Bult, G. J. M. G. Geelen, "An Inherently Linear and Compact MOST-Only Current Division Technique", IEEE Journal of Solid-State Circuits, Vol. 27, pp. 1730-1735, December 1992
• [10] E. A. Vittoz, X. Arreguit, "Linear networks based on transistors", Electronics Letters, Vol. 29, pp. 297-299, February 1993