Low-power open loop multiply-by-two amplifier with gain-accuracy improved by local-feedback

• Autorzy: Gama R. , Galhardo A. , Goes J. , Paulino R. , Neves R. , Horta N.
• Języki publikacji: EN

Abstrakty

EN

This paper proposes the complete electrical design of a new multiply-by-two amplifier to be readily used in ultra high-speed medium resolution pipeline ADC stages. It is based in a switched-capacitor open-loop structure but with the novelty of having the gain accuracy improved by using an active amplifier with local feedback. Simulation results demonstrate that, with a very low-power dissipation and without employing any digital self-calibration or gain-control techniques, the circuit exhibits, over PVT corner and device mismatches, a dynamic performance and a gain-accuracy compatible with 6-bit level.

Słowa kluczowe

EN

ADC (analog to digital converter); multiply by two; low power; time interleaved; gain accuracy

PL

ADC; przetwornik analogowo-cyfrowy; pomnożyć przez dwa; mała moc; przepustowy czas; pozyskiwanie dokładności

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 1
• Strony: 19--24
• Opis fizyczny: Bibliogr. 11 poz.

Twórcy

autor

Gama R.

autor

Galhardo A.

autor

Goes J.

autor

Paulino R.

autor

Neves R.

autor

Horta N.

• DEE/FCT-UNL - CTS/UNINOVA Universidade Nova de Lisboa Monte da Caparica, Portugal,

Bibliografia

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• [2] S. Gupta, et. al., "A IGS/s 11b Time-Interleaved ADC in 0.13um CMOS", Proc. IEEE ISSCC Dig. Tech. Papers, pp. 576-577, Feb. 2006.
• [3] B. Murmann and B. E. Boser, "A 12-bit 75 Ms/s pipelined ADC using open-loop residue amplifier," IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2040-2050, Dee. 2003.
• [4] Ding-L. Shen, Tai-C. Lee, "A 6-bit 800-MS/s Pipelined A/D Converter With Open_Loop Amplifiers", IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 258-268, Feb. 2007.
• [5] K. Poulton, R. Neff, A. Muto, L. Wei, A. Burstein, A., M. Heshami, "A 4 GS/s 8b ADC in 0.35 µm CMOS", Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, vol.1, pp. 166-457, Feb. 2002.
• [6] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 µm CMOS", Solid-State Circuits Conference, Digest of Technical Papers, ISSCC, pp. 318-496, 2003.
• [7] Ja-Hyun Koo, et. Al., "An 8-bit 250MSPS CMOS pipelined ADC using open-loop architecture", IEEE Asia-Pacific Conference, pp. 94-97, August 2004.
• [8] Fan Bing, et. Al., "Modeling and simulation of an open-loop architecture ADC", ASIC, 2007. ASICON '07. 7th International Conference, pp. 1193-1196, October 2007.
• [9] K. Philips, E. Dijkmans, "A Variable Gain IF Amplifier with -67dBc IM3-Distortion at 1.4 Vpp Output in 0.25 µm CMOS", Symposium on VLSI Circuits of Technical Papers, pp. 81-82, June 2001.
• [10] C. Hsu, J.T. Wu, "A Highly Linear 125 JtfHz CMOS Switched-Resistor Programable- Gain Amplifier", IEEE Journal of Solid-State Circuits, vol. 38, pp. 1663-1670, Oct. 2003.
• [11] J. Rijns, "CMOS Low-Distortion High-Frequency Variable-Gain Amplifier", IEEE Journal of Solid-State Circuits, vol. 31, pp. 1029-1034, Oct. 1996.