Design of a novel cascoded CMOS OpAmp with high gain and ± 1.5 V power supply voltage

• Autorzy: Lipka B , Kleine U. , Scheytt J. -C. , Schmalz K.
• Języki publikacji: EN

Abstrakty

EN

The design of a novel CMOS operational amplifier with two differential input stages is described. Prototype circuits have been fabricated and measured successfully. By using a nested Miller compensation the stability of the operational amplifier is ensured. The layout has been created automatically by using the ALADIN tool [6-9]. The small signal model for the amplifier is depicted and the test results are presented.

Słowa kluczowe

EN

low voltage; CMOS operational amplifier; cascoded stage; nested Miller compensation

PL

niskie napięcie; wzmacniacz operacyjny CMOS; stopień kaskodowy; zagnieżdżona kompensacja Millera

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 1
• Strony: 15--18
• Opis fizyczny: Bibliogr. 9 poz.

Twórcy

autor

Lipka B

autor

Kleine U.

autor

Scheytt J. -C.

autor

Schmalz K.

• Otto-von-Guericke University Magdeburg Magdeburg, Germany,

Bibliografia

• [1] D.B Ribner and M.A. Copeland, "Design Techniques for Cascoded CMOS Op Amps with Improved PSRR and Common-Mode Input Range," IEEE J. Solid-State Circuits, vol. SC-19, pp. 919-925, December 1984.
• [2] P.R. Gray and R.G. Meyer, "MOS operational amplifier design - A tutorial overview," IEEE J. Solid-State Circuits, vol. SC-17, pp. 969-982, December 1982.
• [3] K.R. Laker and W.M.C. Sansen, "Design of Analog Integrated Circuits and Systems," McGraw-Hill, Inc. 1994.
• [4] F. Roewer and U. Kleine, "A Novel Class of Complementary Folded-Cascoded Opamps for Low Voltage," IEEE J. Solid-State Circuits, vol. 37, No. 8, pp. 1080-1083, August 2002.
• [5] R.G.H. Eschauzier and J.H. Huijsing, "Fequency Compensation Techniques for Low-Power Operational Amplifiers," Kluwer Academic Publishers, 1995.
• [6] M. Wolf, U. Kleine and B. Hosticka, "A Novel Module Generator Environment," Proc. The European Design & Test Conference, pp. 388-392, March 1996.
• [7] M. Wolf and U. Kleine, "Reliability Driven Module Generation for Analog Layouts," ISCAS 99, vol. 6, pp. 412-415, June 1999.
• [8] L. Zhang, U. Kleine and Y. Jiang, "An Automated Design Tool for Analog Layouts," IEEE Trans. On VLSI, vol. 14, No. 8, pp. 881-894, August 2006.
• [9] B. Lipka and U. Kleine, "Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN," 17th International Workshop PATMOS 2007, pp. 97-106, September 2007.