Analysis and optimization of LUDMOS transistors on a 0.18um SOI CMOS technology

• Autorzy: Toulon G. , Cortés I. , Morancho F. , Villard B.
• Języki publikacji: EN

Abstrakty

EN

This paper is focused on the design and optimization of power LDMOS transistors (V br > 120 Volts) with the purpose of being integrated in a new generation of Smart Power technology based upon a 0.18 μm SOI-CMOS technology. The benefits of applying the shallow trench isolation (STI) concept along with the 3D RESURF concept in the LDMOS drift region is analyzed in terms of the main static (Ron-sp/Vbr tradeoff) and dynamic (Miller capacitance and QgxRon FOM) characteristics. The influence of some design parameters such as the polysilicon gate electrode length and the STI length are exhaustively analyzed.

Słowa kluczowe

EN

power MOSFET; LDMOS; RESURF; STI (shallow trench isolation); superjunction; silicon-on-insulator

PL

moc MOSFET; LDMOS; RESURF; STI (płytki rów izolacyjny); krzem na izolatorze

• Wydawca: Lodz University of Technology. Department of Microelectronics and Computer Science
• Czasopismo: International Journal of Microelectronics and Computer Science
• Rocznik: 2010
• Tom: Vol. 1, nr 1
• Strony: 3--8
• Opis fizyczny: Bibliogr. 16 poz.

Twórcy

autor

Toulon G.

autor

Cortés I.

autor

Morancho F.

autor

Villard B.

• CNRS; LAAS; 7, avenue du Colonel Roche F-31077 Toulousse, France,

Bibliografia

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