Metody symulacji i diagnostyki analogowych układów elektronicznych

• Autorzy: Hałgas S.
• Języki publikacji: PL

Abstrakty

PL

W niniejszej monografii rozpatrzono dwa istotne zagadnienia z zakresu testowania analogowych układów elektronicznych. Przedstawiono trzy nowe metody analizy różnych klas układów nieliniowych, które mogą być wykorzystane w procedurach wspomagających proces diagnostyczny oraz zaproponowano dwie oryginalne metody lokalizacji i identyfikacji wielokrotnych uszkodzeń parametrycznych. W rozdziale pierwszym omówiono aktualny stan wiedzy z zakresu szeroko pojętej diagnostyki układów analogowych, wskazano na najważniejsze nurty badawcze oraz istniejące problemy. W rozdziale drugim, po krótkim wprowadzeniu do zagadnienia szybkiej symulacji obwodów mających zastosowanie w testowaniu, omówiono trzy oryginalne metody w tym zakresie. Pierwsza z nich pozwala w sposób bardzo efektywny wyznaczać rozwiązania stałoprądowe w nieliniowych układach z tranzystorami bipolarnymi w oparciu o idee homotopii oraz algorytm Newtona-Raphsona. Diody występujące w układzie opisano stosując aproksymacje Padego funkcji wykładniczej, wprowadzając jednocześnie do powstałych zależności dyskretny parametr homotopijny. Druga z metod wykorzystuje symulator analizy dynamicznej programu SPICE do wyznaczania charakterystyk parametrycznych w układach stałoprądowych i stanowi alternatywę dla stosowanej standardowo w tym celu analizy DC Sweep programu SPICE, gdzie charakterystyki takie mogą być wyznaczane, ale ze stałym krokiem zmiany wartości rozważanego parametru. Zastosowanie procedur zaimplementowanych w analizie czasowej pozwala obliczać charakterystyki parametryczne ze zmienną długością kroku, co jest znacznie bardziej efektywne i niezawodne. Ostatnia z przedstawionych metod symulacji dotyczy skutecznego przeprowadzania analizy numerycznej w dziedzinie czasu. W tym celu zaproponowano rodzinę liniowych metod dwukrokowych będących kombinacją liniową powszechnie wykorzystywanych w analizie czasowej układów analogowych algorytmów Adamsa-Moultona II rzędu i Geara II rzędu oraz pokazano, że taka kombinacja pozwala zredukować lub uniknąć wad każdej z metod stosowanej oddzielnie. Rozdział trzeci poświęcono zagadnieniom lokalizacji i identyfikacji wielokrotnych uszkodzeń parametrycznych. W pierwszej jego części przedstawiono główne nurty światowych badań w zakresie diagnostyki pojedynczych i wielokrotnych uszkodzeń parametrycznych. Następnie omówiono dwie oryginalne metody diagnostyczne. Pierwsza z nich należy do grupy metod weryfikacyjnych i umożliwia realizację procesu diagnostycznego w liniowych układach stałoprądowych i zmiennoprądowych. Uszkodzenia mogą być też wykrywane, w aspekcie analizy małosygnałowej, w układach nieliniowych, przy założeniu, że przyrządy półprzewodnikowe oraz elementy określające ich punkt pracy są nieuszkodzone lub rzeczywiste wartości parametrów tych elementów zostały wyznaczone przy wykorzystaniu innych metod. W ostatniej części tego rozdziału zaproponowano metodę słownikową pozwalającą identyfikować uszkodzenia parametryczne w układach nieliniowych. Do budowy słownika wykorzystano uogólnioną aproksymacje odcinkowo-liniową charakterystyk parametrycznych otrzymanych na drodze analizy stałoprądowej lub czasowej. Wszystkie zaprezentowane metody zaimplementowano i przetestowano na zbiorze układów elektronicznych zawierających wzmacniacze operacyjne i tranzystory bipolarne. Niektóre z omawianych w pracy metod mogą być też stosowane dla układów z tranzystorami polowymi. Wyniki eksperymentów numerycznych potwierdziły skuteczność rozważanych metod i algorytmów oraz pokazały, że prowadzą one do usprawnienia procesu testowania układów analogowych.

EN

The fundamental problems of testing of analogue electronic circuits are considered in this work. Three methods for the analysis of different classes of nonlinear circuits, which improve the fault diagnosis, are discussed. Two other methods for fault location and identification of multiple soft faults are presented. In the first chapter the state of the art in analogue fault diagnosis is presented, the general problems of automatic testing and the main research areas are indicated. In the second chapter, after the short introduction to the problem of fast fault circuit simulation, three methods in this field are developed. The first method enables us to find efficiently the DC solutions of nonlinear circuits including bipolar transistors. It is based on the homotopy idea and the Newton-Raphson method. All the diodes are described using the Fade approximation formula and the homotopy parameter is introduced inside this formula. The second method uses the transient analysis of SPICE to trace parametric characteristics in DC circuits. It is an alternative approach to the DC Sweep analysis of SPICE, which is able to compute these characteristics, but it uses an inefficient brute-force method with a fixed size of step. The transient analysis employs refined methods, computation techniques and controlling mechanisms, making possible automatic choice and changing the step size during the computation process, so the approach is reliable and more efficient. The last method deals with the transient analysis of nonlinear dynamic circuits by means of numerical integration methods. A new family of two-step second order numerical integration algorithms is developed being a linear combination of the trapezoidal rule and the second-order backward differentiation formula. The proposed method reduces or overcomes the main drawback of the mentioned methods acting alone. The third chapter is devoted to the problem of the location and identification of multiple parametric faults. In the first part the main techniques in the area of the single and multiple soft fault diagnosis are presented. Next two new methods for multiple soft faults are considered. The first one belongs to the verification methods and enables us to identify faults in analogue AC or DC circuits. Although it pertains to linear circuits, some aspects of multiple fault diagnosis of nonlinear circuits can be also performed using the small signal approach. In the next part of the chapter the fault dictionary method is presented. It enables us to identify multiple faults in nonlinear circuits. The dictionary is generated on the basis of the families of parametric characteristics (in DC or time domain), which are described by means of section-wise piecewise-linear functions. All the presented methods have been implemented and tested using several representative examples of practical electronic circuits including operational amplifiers and bipolar transistors. The results of numerical examples show, that they are efficient and improve the testing of analogue circuits.

Słowa kluczowe

PL

układy analogowe; analogowy układ elektroniczny; wielokrotne uszkodzenia parametryczne; symulacja obwodów; diagnostyka analogowych układów elektronicznych

EN

analogue circuits; analogue electronic circuits; multiple parametric faults; circuits simulation; diagnosis in analogue eletronics circuits

• Wydawca: Wydawnictwo Politechniki Łódzkiej
• Czasopismo: Zeszyty Naukowe. Rozprawy Naukowe / Politechnika Łódzka
• Rocznik: 2009
• Tom: Z. 379
• Strony: 3--145
• Opis fizyczny: Bibliogr. 229 poz.

Twórcy

autor

Hałgas S.

• Zakład Elektrotechniki Teoretycznej, Instytut Elektrotechniki Teoretycznej, Metrologii i Materiałoznawstwa, Wydział Elektrotechniki, Elektroniki, Informatyki i Automatyki Politechnika Łódzka,

Bibliografia

• [1] A'ain A. K. B., Bratt A. H., Dorey A. P., Testing analogue circuits by AC power supply voltage, Proceedings of the 9th International Conference on VLSI Design, 238-241, 1996.
• [2] Ahmed S., Cheung P. Y. K., Analog fault diagnosis - a practical approach, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, (1), 351-354, 1994.
• [3] Alippi C., Catelani M., Fort A., Mugnaini M., SET soft fault diagnosis in analog electronic circuits: a sensitivity-based approach by randomized algorithms, IEEE Transactions on Instrumentation and Measurement, (51), 1116-1125, 2002.
• [4] Alippi C., Catelani M., Fort A., Mugnaini M., Automated selection of test frequencies for fault diagnosis in analog electronic circuits, IEEE Transactions on Instrumentation and Measurement, (54), 1033-1044, 2005.
• [5] Aminian F., Aminian M., Fault diagnosis of analog circuits using bayesian neural networks with wavelet transform as preprocessor, Journal of Electronic Testing, (17), 29-36, 2001.
• [6] Aminian F., Aminian M., Fault diagnosis of nonlinear analog circuits using neural networks with wavelet and Fourier transforms as preprocessors, Journal of Electronic Testing, (17), 471-481, 2001.
• [7] Aminian F., Aminian M., Collins H. W., Analog fault diagnosis of actual circuits using neural networks, IEEE Transactions on Instrumentation and Measurement, (51), 544-550, 2002.
• [8] Aminian M., Aminian F., A modular fault-diagnostic system for analog electronic circuits using neural networks with wavelet transform as a preprocessor, IEEE Transactions on Instrumentation and Measurement, (56), 1546-1554, 2007.
• [9] Ashouri M. R., Fault detection of analog circuits using neural networks and Monte-Carlo analysis, Proceedings of the 44th IEEE 2001 Midwest Symposium on Circuits and Systems, MWSCAS 2001, (2), 700-704, 2001.
• [10] Augusto J. S., Almeida C. F. B., Circuit equations for fast fault simulation and diagnosis of linear circuits, Proceedings of the 1998 IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, (1), 125-128, 1998.
• [11] Azais F., Lubaszewski M., Nouet P., Renovell M., A strategy for optimal test point insertion in analog cascaded filters, Journal of Electronic Testing, (21), 9-16, 2005.
• [12] Bandler J. W., Biernacki R. M., Salama A. E., A linear programming approach to fault location in analog circuits, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 1981, 256-260, 1981.
• [13] Bandler J. W., Biernacki R. M., Salama A. E., Starzyk J. A., Fault isolation in linear analog circuits using the L1 norm, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 1982, 1140-1143, 1982.
• [14] Bandler J. W., Salama A. E., Fault diagnosis of analog circuits, Proceedings of the IEEE, (73), 1279-1325, 1985.
• [15] Bhunia S., Roy K., Dynamic supply current testing of analog circuits using wavelet transform, Proceedings of the 20th IEEE VLSI Test Symposium, 302-307, 2002.
• [16] Bhunia S., Raychowdhury J., Roy K., Defect oriented testing of analog circuits using wavelet analysis of dynamic supply current, Journal of Electronic Testing, (21), 147-159, 2005.
• [17] Biernacki R. M., Bandler J. W., Multiple-fault location of analog circuits, IEEE Transactions on Circuits and Systems, (28), 361-367, 1981.
• [18] Bilski P., Wojciechowski J., Automated diagnostics of analog systems using fuzzy logic approach, IEEE Transactions on Instrumentation and Measurement, (56), 2175-2185, 2007.
• [19] Brygilewicz V., Wojciechowski J., Time-domain fault diagnosis of analogue circuits in the presence of noise, IEE Proceedings: Circuits, Devices and Systems, (145), 125-131, 1998.
• [20] Burdiek B., Generation of optimum test stimuli for nonlinear analog circuits using nonlinear programming and time-domain sensitivities, Proceedings of the Design, Automation and Test in Europe, 603-608, 2001.
• [21] Catelani M., Gori M., On the application of neural networks to fault diagnosis of electronic analog circuits, Measurement, (17), 73-80, 1996.
• [22] Catelani M., Fort A., Soft fault detection and isolation in analog circuits: some results and a comparison between a fuzzy approach and radial basis function networks, IEEE Transactions on Instrumentation and Measurement, (51), 196-202, 2002.
• [23] Catelani M., Fort A., Alippi C., A fuzzy approach for soft fault detection in analog circuits, Measurement, (32), 73-83, 2002.
• [24] Cherubal S., Chatterjee A., Parametric fault diagnosis for analog systems using functional mapping, Proceedings of the Design, Automation and Test in Europe, 195-200, 1999.
• [25] Cherubal S., Chatterjee A., Test generation based diagnosis of device parameters for analog circuits, Proceedings of the Design, Automation and Test in Europe, 596-602,2001.
• [26] Chruszczyk Ł., Grzechca D., Rutkowski J., Finding of optimal excitation signal for testing of analog electronic circuits, Bulletin of the Polish Academy of Sciences, Technical Sciences, (55), 273-280, 2007.
• [27] Chua L. O., Lin P. M., Komputerowa analiza układów elektronicznych. Algorytmy i metody obliczeniowe, WNT, Warszawa, 1981.
• [28] Chua L. O., Kang S. M., Section-wise piecewise-linear functions: Canonical representation, properties, and applications, Proceedings of IEEE, (65), 915-929, 1977.
• [29] Cota E. F., Negreiros M., Carro L., Lubaszewski M., A new adaptive analog test and diagnosis system, IEEE Transactions on Instrumentation and Measurement, (49), 223-227, 2000.
• [30] Czaja Z., Zielonko R., Fault diagnosis in electronic circuits based on bilinear transformation in 3-D and 4-D spaces, IEEE Transactions on Instrumentation and Measurement, (52),97-102,2003.
• [31] Czaja Z., Zielonko R., On fault diagnosis of analogue electronic circuits based on transformation in multi-dimensional spaces, Measurement, (35), 293-301, 2004.
• [32] Czaja Z., Using a square-wave signal for fault diagnosis of analog parts of mixed-signal embedded systems controlled by microcontrollers, Proceedings of the 2007 IEEE Instrumentation and Measurement Technology Conference, CDROM, 2007.
• [33] Czaja Z., Załęski D., Employing a fuzzy logic based method to the fault diagnosis of analog parts of electronic embedded systems, Proceedings of the 2007 IEEE Instrumentation and Measurement Technology Conference, CDROM, 2007.
• [34] Czaja Z., Using a square-wave signal for fault diagnosis of analog parts of mixed-signal electronic embedded systems, IEEE Transactions on Instrumentation and Measurement, (57), 1589-1595,2008.
• [35] Dai H., Souders T. M., Time-domain testing strategies and fault diagnosis for analog systems, Proceedings of the 6th IEEE Instrumentation and Measurement Technology Conference, IMTC-89, 293-298, 1989.
• [36] Dai H., Souders T. M., Time-domain testing strategies and fault diagnosis for analog systems, IEEE Transactions on Instrumentation and Measurement, (39), 157-162, 1990.
• [37] Dobrowolski A., Pod maską SPICE'a, ETC, Warszawa, 2004.
• [38] Duhamel P., Rault J. C., Automatic test generation techniques for analog circuits and systems: A review, IEEE Transactions on Circuits and Systems, (26), 411-440, 1979.
• [39] Fedi G., Giomi R., Manetti S., Piccirilli M. C., A symbolic approach for testability evaluation in fault diagnosis of nonlinear analog circuits, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS 1998, (6), 9-12, 1998.
• [40] Fedi G., Giomi R., Luchetta A., Manetti S., Piccirilli M. C., On the application of symbolic techniques to the multiple fault location in low testability analog circuits, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, (45), 1383-1388, 1998.
• [41] Fedi G., Luchetta A., Manetti S., Piccirilli M. C., A new symbolic method for analog circuit testability evaluation, IEEE Transactions on Instrumentation and Measurement, (47), 554-565, 1998.
• [42] Fedi G., Manetti S., Piccirilli M. C., Starzyk J. A., Determination of an optimum set of testable componenets in the fault diagnosis of analog linear circuits, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (46), 779-787, 1999.
• [43] Fenton W. G., McGinnity T. M., Maguire L. P., Fault diagnosis of electronic systems using intelligent techniques: A review, IEEE Transactions on Systems, Man., and Cybernetics - Part C: Applications and Reviews, (31), 269-281, 2001.
• [44] Filippetti F., Artioli M., Single and multiple fault diagnosis based on symbolic analysis and reduced set of observable points for linear analog circuits, Proceedings of the 7th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2000, (1), 433-436, 2000.
• [45] Gizopoulos D. ed., Advances in electronic testing. Challenges and methodologies, Springer, Dordrecht, 2006.
• [46] Gładysz H., Peciakowski E., Niezawodność elementów elektronicznych, WKL, Warszawa, 1984.
• [47] Golonek T., Rutkowski J., Application of genetic programming to analog fault decoder design, Proceedings of the European Conference on Circuit Theory and Design, EC-CTD2003, (2), 113-116,2003.
• [48] Golonek T., Grzechca D., Rutkowski J., Ewolucyjny dobór częstotliwości sygnałów testujących z rozmytą inicjacją systemu, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 101-106, 2007.
• [49] Golonek T., Rutkowski J., Genetic-algorithm-based method for optimal analog test points selection, IEEE Transactions on Circuits and Systems II: Express Briefs, (54), 117-121,2007.
• [50] Grasso F., Luchetta A., Manetti S., Piccirilli M. C., Symbolic techniques for the selection of test frequencies in analog fault diagnosis, Analog Integrated Circuits and Signal Processing, (40), 205-213, 2004.
• [51] Grasso F., Luchetta A., Manetti S., Piccirilli M. C., A method for the automatic selection of test frequencies in analog fault diagnosis, IEEE Transactions on Instrumentation and Measurement, (56), 2322-2329, 2007.
• [52] Grzechca D., Rutkowski J., Fuzzy rule expert system to analog fault diagnosis, Proceedings of the 1st International Conference Signals and Electronic Systems, ICSES 2000, 509-514,2000.
• [53] Grzechca D., Rutkowski J., Analog fault dictionary - fuzzy set approach, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2001, 249-252, 2001.
• [54] Grzechca D., Rutkowski J., Use of sensitivity matrix and fuzzy set theory to analog fault detection, Proceedings of the International Conference on Signals and Electronic Systems, ICSES 2001, 349-355, 2001.
• [55] Grzechca D., Rutkowski J., Adaptive algorithm for analog fault based on a sensitivity matrix and the fuzzy set theory, Proceedings of the 9th International Conference on Electronics, Circuits and Systems, ICECS 2002, (2), 649-652, (2002).
• [56] Grzechca D., Rutkowski J., Use of neural network and fuzzy logic to time domain analog testing, Proceedings of the 9th International Conference on Neural Information Processing, ICONIP '02, (5), 2601-2604, 2002.
• [57] Grzechca D., Rutkowski J., Creation of analog fault AC dictionary based on fuzzy-neural network and output coding, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2003, (2), 237-240, 2003.
• [58] Grzechca D., Rutkowski J., New concept to analog fault diagnosis by creating two fuzzy-neutral dictionaries test, Proceedings of the 12th IEEE Mediterranean Electrotechnical Conference, MELECON 2004, (1), 115-118, 2004.
• [59] Grzechca D., Rutkowski J., Use of neuro-fuzzy system to time domain electronic circuits fault diagnosis, Proceedings of the 2005 ICSC Congress on Computational Intelligence Methods and Applications, 2005.
• [60] Grzechca D., Golonek T., Rutkowski J., Wykorzystanie metody symulowanego wyżarzania do doboru optymalnego pobudzenia testującego analogowe układy elektroniczne, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 83-88, 2007.
• [61] Grzechca D., Golonek T., Rutkowski J., The use of simulated annealing with fuzzy objective function to optimal frequency selection for analog circuit diagnosis, Proceedings of the 14th IEEE International Conference on Electronics, Circuits and System, ICECS 2007, 899-902, 2007.
• [62] Guo Z., Savir J., Coefficient-based test of parametric faults in analog circuits, IEEE Transactions on Instrumentation and Measurement, (55), 150-157, 2006.
• [63] Hałgas S., Algorytm lokalizacji uszkodzeń w nieliniowych układach elektronicznych, Materiały XVI Seminarium z Podstaw Elektrotechniki i Teorii Obwodów, SPETO'93, 247-253, 1993.
• [64] Hałgas S., An algorithm for fault location and parameter identification of analog circuits based on interval arithmetics, Proceedings of the XVI-th National Conference: Circuit Theory and Electronic Circuits, KKTOiUE'93, 223-228, 1993.
• [65] Hałgas S., An algorithm for fault location and parameter identification of analog circuits based on interval arithmetics, Bulletin of the Polish Academy of Sciences, Technical Sciences, (42), 75-81, 1994.
• [66] Hałgas S., Zastosowanie analizy wrażliwościowej w lokalizacji uszkodzeń, Materiały XVII Seminarium z Podstaw Elektrotechniki i Teorii Obwodów, SPETO'94, 359-364, 1994.
• [67] Hałgas S., Wielowymuszeniowa metoda identyfikacji parametrów w elektronicznych układach prądu stałego, Materiały XVIII Seminarium z Podstaw Elektrotechniki i Teorii Obwodów, SPETO'95, 231-237, 1995.
• [68] Hałgas S., Metoda słownikowa lokalizacji uszkodzeń i identyfikacji parametrów w układach nieliniowych, Materiały XIX Seminarium z Podstaw Elektrotechniki i Teorii Obwodów, SPETO'96, 413-416, 1996.
• [69] Hałgas S., Zastosowanie metod teorii obwodów w diagnostyce uszkodzeń stałoprądowych układów elektronicznych, Rozprawa doktorska, Łódź, 1998.
• [70] Hałgas S., Nowa metoda lokalizacji uszkodzeń w tranzystorowych układach bipolarnych, Materiały XXIII Międzynarodowej Konferencji z Podstaw Elektrotechniki i Teorii Obwodów, IC-SPETO'2000, 297-300, 2000.
• [71] Hałgas S., Metoda słownikowa wykrywania uszkodzeń parametrycznych w układach nieliniowych, Materiały VI Krajowej Konferencji Elektroniki, KKE'07, (1), 119-124, 2007.
• [72] Hałgas S., Multiple soft fault diagnosis of nonlinear circuits using the fault dictionary approach, Bulletin of the Polish Academy of Sciences, Technical Sciences, (56), 53-57, 2008.
• [73] Hałgas S., Tadeusiewicz M., Multiple soft fault diagnosis of analogue electronic circuits, Proceedings of the International Conference on Signals and Electronic Systems, ICSES'08, 533-536, 2008.
• [74] Hamida N. B., Kaminska B., Analog circuit testing based on sensitivity computation and new circuit modeling, Proceedings of the International Test Conference, ITC'93,652-661, 1993.
• [75] Hatzopoulos A. A., Kontoleon J. M., Fault diagnosis in large analogue circuits based on hybrid decomposition, IEE Proceedings G: Circuits, Devices and Systems, (139), 311-318, 1992.
• [76] Hatzopoulos A. A., Iatrou E., Katsaras C., Papakostas D. K., Testing of analogue and mixed-signal circuits by using supply current measurements, IEE Proceedings: Circuits, Devices and Systems, (145), 319-324, 1998.
• [77] Hauseholder A. S., The theory of matrices in numerical analysis, Blaisded Publishing Company, New York, 1965.
• [78] He Y. G., Tan Y. H., Sun Y., A neural network approach for fault diagnosis of large-scale analogue circuits, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2002, (1), 153-156, 2002.
• [79] He Y. G., Tan Y. H., Sun Y., Wavelet neural network approach for fault diagnosis of analogue circuits, IEE Proceedings - Circuits, Devices and Systems, (151), 379-384,2004.
• [80] Hochwald W., Bastian J. D., A dc approach for analog fault dictionary determination, IEEE Transactions on Circuits and Systems, (26), 523-529, 1979.
• [81] Hou J., Chatterjee A., Analog transient concurrent fault simulation with dynamic fault grouping, Proceedings of the 2000 International Conference on Computer Design, 35-41, 2000.
• [82] http://mathworld. wolfram. com/PadeApproximant. html
• [83] Huang Z. E, Lin C. S., Liu R. W., Node-fault diagnosis and a design of testability, IEEE Transactions on Circuits and Systems, (30), 257-265, 1983.
• [84] ICAP/4 - IsSpice 4 user's guide, Intusoft, 1998.
• [85] Jagodnik J., Wolfson M., Systematic fault simulation in an analog circuit simulator, IEEE Transactions on Circuits and Systems, (26), 549-554, 1979.
• [86] Jantos D., Grzechca D., Golonek T., Rutkowski J., Zastosowanie programowania wyrażeń genetycznych do wyboru optymalnego zbioru częstotliwości w diagnostyce analogowych uktadów elektronicznych, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 143-148, (2007).
• [87] Jantos D., Grzechca D., Golonek T., Rutkowski J., Heuristic methods to test frequencies optimization for analogue circuit diagnosis. Bulletin of the Polish Academy of Sciences, Technical Sciences, (56), 29-38, 2008.
• [88] Johnson A., Efficient fault analysis in linear analog circuits, IEEE Transactions on Circuits and Systems, (26), 475-484, 1979.
• [89] Kabisatpathy P., Barua A., Sinha S., Fault diagnosis of analog integrated circuits, Springer, Dordrecht, 2005.
• [90] Kaminska B., Arabi K., Bell I., Goteti P., Huertas J. L., Kim B., Rueda A., Soma M., Analog and Mixed-Signal Benchmark Circuits - First Release, Proceedings of the 1997 IEEE International Test Conference, 183-190, 1997.
• [91] Khouas A., Derieux A., Fault simulation for analog circuits under parameter variations, Journal of Electronic Testing, (16), 269-278, 2000.
• [92] Kielkowski R. M. Inside SPICE, McGraw-Hill, New York, 1998.
• [93] Kondagunturi R., Bradley E., Maggard K., Stroud C., Benchmark circuits for analog and midex-signal testing, Proceedings of the IEEE Southeastconf'99, 217-220, 1999.
• [94] Korzybski M., Opracowanie metod diagnostyki układów elektronicznych z wykorzystaniem technik ewolucyjnych , Rozprawa doktorska, Łódź, 2007.
• [95] Korzybski M., Zastosowanie metody ewolucyjnej do lokalizacji i identyfikacji uszkodzeń, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 169-174, 2007.
• [96] Korzybski M., Ossowski M., The selection of genetic algorithm parameters for soft fault diagnosis, Przeglqd Elektrotechniczny - Konferencje, (2), 272-275, 2007.
• [97] Korzybski M., Dictionary method for multiple soft and catastrophic fault diagnosis based on evolutionary computation, Proceedings of the International Conference on Signals and Electronic Systems, ICSES'08, 553-556, 2008.
• [98] Koszlaga J., Strumiłło P. Discovery of linguistic rules by means of RBF network for fault detection in electronic circuits, Proceedings of 7th International Conference Artificial Intelligence and Soft Computing, ICAISC 2004, 223-228, 2004.
• [99] Kuczyński A., Ossowski M., Poprawa skuteczności wykrywania uszkodzeń katastroficznych w układach analogowych, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 175-180,2007.
• [100] Kurowski I., Rutkowski J., Wykorzystanie neuronowych sieci modularnych do diagnostyki analogowych układów elektronicznych, Materiały VI Krajowej Konferencji Elektroniki, KKE 2007, (1), 71-76, 2007.
• [101] Laknaur A., Rui Xiao, Haibo Wang, A programmable window comparator for analog online testing, Proceedings of the 25th IEEE VLSI Test Symposium, 119-124, 2007.
• [102] Leung K. H., Spence R., Multiparameter large-change sensitivity analysis and systematic exploration, IEEE Transactions on Circuits and Systems, (22), 796-704, 1975.
• [103] Li F., Woo P.-Y., The invariance of node-voltage sensitivity sequence and its application in a unified fault detection dictionary method, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (46), 1222-1226, 1999.
• [104] Li F., Woo P.-Y., Fault detection for linear 1C - the method of short-circuits admittance parameters, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (49), 105-108, 2002.
• [105] Lin J. W., Lee Ch. L., Fault diagnosis for linear analog circuits, Journal of Electronic Testing, (17), 483-494, 2001.
• [106] Liu D., Starzyk J. A., A generalized fault diagnosis in dynamic analog circuits, International Journal of Circuit Theory and Applications, (30), 487-510, 2002.
• [107] Macura A., Zastosowanie metody potencjałów węzłowych do lokalizacji i identyfikacji uszkodzeń, Materiały XI Krajowej Konferencji: Teoria Obwodów i Układy Elektroniczne, KKTOiUE'88, 220-225, 1988.
• [108] Macura A., Rutkowski J., Lokalizacja i identyfikacja uszkodzeń w obwodach analogowych, Materiały XIII Krajowej Konferencji: Teoria Obwodów i Układy Elektroniczne, KKTOiUE'90, 81-86, 1990.
• [109] Manetti S., Piccirilli M. C., Liberatore A., Automatic test point selection for linear analog network fault diagnosis, Proceedings of the International Symposium on Circuit and Systems, ISCAS'90, (1), 25-28, 1990.
• [110] Manetti S., Piccirilli M. C., A singular-value decomposition approach for ambiguity group determination in analog circuits, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (5), 477-487, 2003.
• [111] Materka A., Fast and accurate identification of electronic circuit parameters using regularised feedforward neural networks, Proceedings of the 1993 International Joint Conference on Neural Networks, IJCNN'93, (1), 509-512, 1993.
• [112] Materka A., Neural network technique for parametric testing of mixed-signal circuits, Electronics Letters, (31), 183-184, 1995.
• [113] Materka A., New technique for analog circuit parameter identification using neural-network-based approximators, Proceedings of the XVHI-th National Conference: Circuit Theory and Electronic Circuits, KKTOiUE'95,407-412, 1995.
• [114] Materka A., Parametric fault identification in mixed-signal circuits using feedforward neural networks, 2nd Advanced Training Course MIXED DESIGN OF VLSI CIRCUITS, 84-89, 1995.
• [115] Materka A., Strzelecki M., Parametric testing of CMOS circuits by ANN-based processing of transient power supply current, Proceedings of the IEEE International Mixed-Signal Testing Workshop, 223-227, 1995.
• [116] Materka A., Strzelecki M., Parametric testing of mixed-signal circuits by ANN processing of transient responses, Journal of Electronic Testing, (9), 187-202, 1996.
• [117] McKeon A., Wakeling A., Fault diagnosis in analogue circuits using AI techniques, Proceedings of the International Test Conference, ITC'89, 118-123, 1989.
• [118] McKeon A., Wakeling A., The automatic diagnosis of faults in analogue and mixed-signal circuits, Proceedings of the European Conference on Design Automation, EDAC'91, 89-93, 1991.
• [119] Milor L. S., A tutorial introduction to research on analog and mixed-signal circuit testing, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, (45), 1389-1407, 1998.
• [120] Mir S., Lubaszewski M., Kolarik V.; Courtois B., Automatic test generation for maximal diagnosis of linear analog circuits, Proceedings of the European Design and Test Conference, ED&TC 96, 254-258, 1996.
• [121] Miura Y., Kato J., Fault diagnosis of analog circuits based on adaptive test and output characteristics, Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 410-418, 2006.
• [122] Mosin S. G., Neural network based technique for detecting catastrophic and parametric faults in analog circuits, Proceedings of the 18th International Conference on Systems Engineering, ICSEng 2005, 224-229, 2005.
• [123] Nagi N., Chatterjee A., Balivada A., Abraham J. .A., Efficient multisine testing of analog circuits, Proceedings of the 8th International Conference on VLSI Design, 234-238, 1995.
• [124] Navid N., Willson A., A theory and an algorithm for analog circuit fault diagnosis, IEEE Transactions on Circuits and Systems, (26), 440-457, 1979.
• [125] Ogg S., Lesage S., Jervis B. W., Maiden Y., Zimmer T., Multiple fault diagnosis in analogue circuits using time domain response features and multilayer perceptrons, IEE Proceedings - Circuits, Devices and Systems, (145), 213-218, 1998.
• [126] Ogrodzki J., Komputerowa analiza układów elektronicznych, PWN, Warszawa, 1994.
• [127] Osowski S., Markiewicz T., Sałat R., Parametric fault location of electrical circuit using Support Vector Machine, 18th IMEKO World Congress Metrology for a Sustainable Development, 342-347, 2006.
• [128] Osowski S., Modelowanie i symulacja układów i procesów dynamicznych, Oficyna Wydawnicza Politechniki Warszawskiej, Warszawa, 2007.
• [129] Ozawa T., Kajitani Y., Diagnosability of linear active networks, IEEE Transactions on Circuits and Systems, (26), 485-489, 1979.
• [130] Ozawa T., Analog methods for computer - aided circuit analysis and diagnosis, M. Dekker, New York, 1988.
• [131] Pahwa A., Rohrer R. A., Band faults: Efficient approximations to fault bands for the simulation before fault diagnosis of linear circuits, IEEE Transactions on Circuits and Systems, (29), 81-88, 1982.
• [132] Pang J., Starzyk J. A., Fault diagnosis in mixed-signal low testability system, International Journal of Analog Integrated Circuits and Signal Processing, (28), 159-170, 2001.
• [133] Porębski J., Korohoda P., SPICE - program analizy nieliniowej układów elektronicznych, WNT, Warszawa, 1996.
• [134] Prasad V. C., Pinjala S. N. R., Boolean method for selection of minimal set of test nodes for analogue fault dictionary, Electronics Letters, (29), 747-749, 1993.
• [135] Prasad V. C., Pinjala S. N. R., Fast algorithms for selection of test nodes of an analog circuit using a generalized fault dictionary approach, Circuits, Systems Signal Processing, (14), 707-724, 1995.
• [136] Prasad V. C., Babu N. S. C., On minimal set of test nodes for fault dictionary of analog circuit fault diagnosis, Journal of Electronic Testing: Theory and Applications, (7), 255-258, 1995.
• [137] Prasad V. C., Babu N. S. C., Selection of test nodes for analog fault diagnosis in dictionary approach, IEEE Transactions on Instrumentation and Measurement, (49), 1289-1297,2000.
• [138] Pułka A., Rutkowski J., A common-sense based approach to the automated test-point selection in fault diagnosis, Proceedings of the 2007 European Conference on Circuit Theory and Design, ECCTD 2007, 838-841, 2007.
• [139] Quarles T. L., Newton A. R., Pederson D. O., Sangiovanni-Vincentelli A., SPICE-3 Version 3F5 User's Manual, Berkeley, California, 1994.
• [140] Qu Haini, Xu Weisheng, Yu Youling, Design of neural network output layer in fault diagnosis of analog circuit, Proceedings of the 8th International Conference on Electronic Measurement and Instruments, ICEMF07, (3), 639-642, 2007.
• [141] Robotycki A., Zielonko R., Some models and methods for fault diagnosis of analog piecewise linear circuits via verification technique, Proceedings of the 17th IEEE Instrumentation and Measurement Technology Conference, IMTC 2000, (2), 1050-1055, 2000.
• [142] Robotycki A., Zielonko R., Fault identification in analog PWL circuits based on homotopy, Proceedings of the 18th IEEE Instrumentation and Measurement Technology Conference, IMTC 2001, (1), 59-64, 2001.
• [143] Robotycki A., Zielonko R., Fault diagnosis of analog piecewise linear circuits based on homotopy, IEEE Transactions on Instrumentation and Measurement, (51), 876-881, 2002.
• [144] Rutkowski J., Macura A., Fault location for nonlinear resistive circuits, Electronic Letters, (20), 401 -403, 1984.
• [145] Rutkowski J., Macura A., Multiple fault location in ac circuits, IEE Proceedings, Pt G, (133), 279-284, 1986.
• [146] Rutkowski J., Diagnostyka dużych analogowych układów elektronicznych z zastosowaniem metod topologicznych, Zeszyty Naukowe Politechniki Śląskiej, Z. 105, Gliwice, 1991.
• [147] Rutkowski J., Neural network approach to fault location in nonlinear DC circuits, Proceedings of the XIV Conference Circuit Theory and Electronic Circuits, 568-573, 1991.
• [148] Rutkowski J., A DC fault dictionary approach to analog fault diagnosis, Proceedings of the XV Conference Circuit Theory and Electronic Circuits, 151-156, 1992.
• [149] Rutkowski J., A neural network approach to fault location in nonlinear DC circuits, Proceedings of the 1 st International Conference Artificial Neural Networks, 1123-1126, 1992.
• [150] Rutkowski J., A DC approach for analog fault dictionary determination, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'93, 877-880, 1993.
• [151] Rutkowski J., Decomposition approach to analog fault location, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'93, 881-884, 1993.
• [152] Rutkowski J., A two stage neural network DC fault dictionary, Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, (6), 299-302, 1994.
• [153] Rutkowski J., The DC fault dictionary - a neural network approach, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'95, 295-298, 1995.
• [154] Rutkowski J., Słownikowe metody diagnostyczne analogowych układów elektronicznych, WKL, Warszawa, 2003.
• [155] Rutkowski J., Słownikowe metody diagnostyczne analogowych układów elektronicznych, Elektronika, (12), 33-37, 2004.
• [156] Rutkowski J., Applying artificial intelligence techniques to analog fault detection and classification, Zeszyty Naukowe Wydziału ETI Politechniki Gdańskiej, 15-24, 2005.
• [157] Rutkowski J., Machniewski J., Sensitivity based analog fault dictionary, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'99, 589-602, 1999.
• [158] Rutkowski J., Machniewski J., Description of the dc fault dictionary in the measurement space, Proceedings of the European Conference on Circuit Theory and Design, ECCTD'99, 243-246, 1999.
• [159] Rutkowski J., Machniewski J., Integer-code DC fault dictionary, Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, ISCAS 2000, (5), 713-716, 2000.
• [160] Rutkowski J., Puchalski B., Optimum test selection for analog circuits with the use of information channel concept, Proceedings of the International Conference on Signals and Electronic Systems, ICSES 2002, 325-330, 2002.
• [161] Salama A. E., Bandler J. W., Starzyk J. A., A unified decomposition approach for fault location in large analog circuits, IEEE Transactions on Circuits and Systems, (31), 609-622, 1984.
• [162] Sałat R., Osowski S., Siwek K., Principal component analysis for feature selection at the diagnosis of electrical circuits, Przeglqd Elektrotechniczny, 667-670, 2003.
• [163] Sałat R., Osowski S., Analog filter diagnosis using Support Vector Machine, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2003, (3), 421-424, 2003.
• [164] Savir J., Guo Z., On the detectability of parametric faults in analog circuits, Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 273-276, 2002.
• [165] Schreiber H. H., Fault dictionary based upon stimulus design, IEEE Transactions on Circuits and Systems, (26), 529-537, 1979.
• [166] Sen N., Saeks R., Fault diagnosis for linear systems via multifrequency measurements, IEEE Transactions on Circuits and Systems, (26), 457-465, 1979.
• [167] Shi C. J., Tian M. W., Shi G., Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (25), 1392-1400, 2006.
• [168] Slamani M., Kaminska B., Analog circuit fault diagnosis based on sensitivity computation and functional testing, IEEE Design and Test of Computers, (9), 30-39, 1992.
• [169] Slamani M., Kaminska B., Multifrequency testability analysis for analog circuits, Proceedings of the 12th IEEE VLSI Test Symposium, 54-59, 1994.
• [170] Slamani M., Kaminska B., Fault observability analysis of analog circuits in frequency domain, IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, (43), 134-139, 1996.
• [171] Song G., Wang H., Jiang S., Liu H., Fault diagnosis approach of analog circuits based on genetic wavelet neural network, Proceedings of the 18th International Conference on Electronic Measurement and Instruments, ICEMI '07, (3), 675-679, 2007.
• [172] Somayajula S. S., Sanchez-Sinencio E., Pineda de Gyvez J., A power supply ramping and current measurement based technique for analog fault diagnosis, Proceedings of the 12th IEEE VLSI Test Symposium, 234-239, 1994.
• [173] Spinks S. J., Chalk C. D., Bell I. M., Zwolinski M., Generation and verification of tests for analog circuits subject to process parameter deviations, Journal of Electronic Testing, (20), 11-23,2004.
• [174] Starzyk J. A., Dai H., A decomposition approach for testing large analog networks, Journal of Electronic Testing: Theory and Applications, (3), 181-195, 1992.
• [175] Starzyk J. A., Pang J., Manetti S., Piccirilli M. C., Fedi G., Finding ambiguity groups in low testability analog circuits, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, (47), 1125-1137, 2000.
• [176] Starzyk J. A., Pang J., Fault diagnosis in analog and mixed mode low testability systems, Proceedings of the 2000 IEEE International Symposium on Circuits and Systems, ISCAS 2000, 649-652, 2000.
• [177] Starzyk J. A., Liu D., A method for multiple fault diagnosis in analog circuits, Proceedings of the 33rd Southeastern Symposium on System Theory, 65-68, 2001.
• [178] Starzyk J. A., Liu D., Multiple fault diagnosis of analog circuits based on large change sensitivity analysis, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2001, (1), 241-244, 2001.
• [179] Starzyk J. A., Liu D., Multiple fault diagnosis of analog circuits by locating ambiguity groups of test equation, Proceedings of the 2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001, (5), 199-202, 2001.
• [180] Starzyk J. A., Liu D., Liu Z., Nelson D. E., Rutkowski J., Entropy-based optimum test points selection for analog fault dictionary techniques, IEEE Transactions on Instrumentation and Measurement, (53), 754-761, 2004.
• [181] Stenbakken G. N., Souders T. M., Stewart G. W., Ambiguity groups and testability, IEEE Transactions on Instrumentation and Measurement, (38), 941-947, 1989.
• [182] Sun Y., Chen G., Li H., Analog circuits fault diagnosis based on support vector machine, Proceedings of the 8th International Conference on Electronic Measurement and Instruments, ICEMI'07, (3), 630-634, 2007.
• [183] Sun Y., Chen G., Li H., Analog circuits fault diagnosis using support vector machine, Proceedings of the International Conference on Communications, Circuits and Systems, ICCCAS 2007, 1003-1006, 2007.
• [184] Tadeusiewicz M., A-stabilne metody analizy obwodów dynamicznych, Archiwum Elektrotechniki, (3), 689-700, 1980.
• [185] Tadeusiewicz M., Metody komputerowej analizy stałoprqdowej nieliniowych układów elektronicznych, WNT, Warszawa, 1991.
• [186] Tadeusiewicz M., Hałgas S., Continuation algorithms for solving nonlinear resistive circuits, Proceedings of the XV-th National Conference: Circuit Theory and Electronic Circuits, KKTOiUE'92, 42-47, 1992.
• [187] Tadeusiewicz M., Hałgas S., DC analysis of nonlinear electronic circuits via homotopy approach, Zeszyty Naukowe Politechniki Łódzkiej, Elektryka, (87), 77-87, 1994.
• [188] Tadeusiewicz M., Korzybski M., A method for fault diagnosis in linear electronic circuits, International Journal of Circuit Theory and Applications, (28), 245-262, 2000.
• [189] Tadeusiewicz M., Hałgas S., An algorithm for soft fault diagnosis of DC circuits, Proceedings of the 15th European Conference on Circuit Theory and Design, ECCTD'0l, (1), 245-248,2001.
• [190] Tadeusiewicz M., Hałgas S., Soft fault diagnosis of nonlinear DC circuits, Proceedings of the International Conference on Signals and Electronic Systems, ICSES'2001, 341-347, 2001.
• [191] Tadeusiewicz M., Hałgas S., Korzybski M., An algorithm for soft-fault diagnosis of linear and nonlinear circuits, IEEE Transactions on Circuits and Systems -1: Fundamental Theory and Applications, (49), 1648-1653, 2002.
• [192] Tadeusiewicz M., Hałgas S., Transient analysis of nonlinear dynamic circuits using a numerical-integration method, Proceedings of XII International Symposium on Theoretical Electrical Engineering, ISTET'2003, (1), 131-134, 2003.
• [193] Tadeusiewicz M., Hałgas S., An algorithm for the analysis of dynamic electronic circuits, Proceedings of VI th International Workshop: Computational Problems of Electrical Engineering, CPEE'2004, 221-224, 2004.
• [194] Tadeusiewicz M., Hałgas S., Computing multivalued input-output characteristics in the circuits containing bipolar transistors, IEEE Transactions on Circuits and Systems - I: Regular Papers, (51), 1859-1867, 2004.
• [195] Tadeusiewicz M., Hałgas S., Transient analysis of nonlinear dynamic circuits using a numerical-integration method, COMPEL: International Journal for Computation and Mathematics in Electrical and Electronic Engineering, (24), 707-719, 2005.
• [196] Tadeusiewicz M., Hałgas S., Evaluation of the faulty parameters of analog circuits, Proceedings of XIII International Symposium on Theoretical Electrical Engineering, ISTET 2005, 384-387, 2005.
• [197] Tadeusiewicz M., Hałgas S., Sidyk P., Building and exploiting fault dictionary for transistor circuits diagnosis, Proceedings of XIII International Symposium on Theoretical Electrical Engineering, ISTET 2005, 388-391, 2005.
• [198] Tadeusiewicz M., Hałgas S., Multiple fault diagnosis in analogue circuits, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2005, (3), 205-208, 2005.
• [199] Tadeusiewicz M., Hałgas S., Diagnostyka układów elektronicznych z wielokrotnymi uszkodzeniami, Materiały XXIX Międzynarodowej Konferencji z Podstaw Elektrotechniki i Teorii Obwodów, IC-SPETO'2006, (2), 279-282, 2006.
• [200] Tadeusiewicz M., Sidyk P., Tracing parametric characteristics in nonlinear circuits using SPICE-oriented approach, Materiały XXIX Międzynarodowej Konferencji z Podstaw Elektrotechniki i Teorii Obwodów, IC-SPETO'2006, (2), 283-286, 2006.
• [201] Tadeusiewicz M., Hałgas S., An algorithm for multiple fault diagnosis in analogue circuits, International Journal of Circuit Theory and Applications, (34), 607-615, 2006.
• [202] Tadeusiewicz M., Sidyk P., Hałgas S., A method for multiple fault diagnosis in dynamic analogue circuits, Proceedings of the European Conference on Circuit Theory and Design, ECCTD 2007, 834-837, 2007.
• [203] Tadeusiewicz M., Hałgas S., Finding operating points of the diode-transistor circuits via homotopy approach, Przeglqd Elektrotechniczny - Konferencje, (2), 69-72, 2007.
• [204] Tadeusiewicz M., Hałgas S., Sidyk P., Metoda wykrywania uszkodzeń parametrycznych w układach tranzystorowych, Elektronika - Konstrukcje, Technologie, Zastosowania, (11), 31-33,2007.
• [205] Tadeusiewicz M., Hałgas S., Komputerowe metody analizy układów analogowych: Teoria i zastosowania, WNT, Warszawa, 2008.
• [206] Tadeusiewicz M., Hałgas S., Wyznaczanie statycznych charakterystyk w układach tranzystorowych z wykorzystaniem symulatora analizy dynamicznej SPICE, Materiały VII Krajowej Konferencji Elektroniki, KKE'08, (2), 349-354, 2008.
• [207] Tadeusiewicz M., Hałgas S., Zastosowanie koncepcji homotopii do analizy DC układów tranzystorowych z uwzględnieniem zjawiska samonagrzewania, Materiały VII Krajowej Konferencji Elektroniki, KKE'08, (2), 361-366, 2008.
• [208] Tadeusiewicz M., Hałgas S., Wyznaczanie statycznych charakterystyk w układach tranzystorowych z wykorzystaniem symulatora analizy dynamicznej SPICE, Elektronika -Konstrukcje, Technologie, Zastosowania, (11), 170-173, 2008.
• [209] Tadeusiewicz M., Hałgas S., Zastosowanie koncepcji homotopii do analizy DC układów tranzystorowych z uwzględnieniem zjawiska samonagrzewania, Elektronika - Konstrukcje, Technologie, Zastosowania, (11), 140-144, 2008.
• [210] Tadeusiewicz M., Hałgas S., A method for fast simulation of multiple catastrophic faults in analogue circuits, International Journal of Circuit Theory and Applications, stron 16, przyjęto do druku.
• [211] Temes G. C., Efficient methods of fault simulation, Proceedings of the 20th Midwest Symposium on Circuits and Systems, 191-194, 1977.
• [212] Tian M. W., Shi R. C. J., Rapid frequency-domain analog fault simulation under parameter tolerances, Proceedings of the 34th Design Automation Conference, 275-280, 1997.
• [213] Tian M. W., Shi R. C. J., Nonlinear analog DC fault simulation by one-step relaxation, Proceedings of the 16th IEEE VLSI Test Symposium, 126-131, 1998.
• [214] Tian M. W., Shi R. C. J., Worst case tolerance analysis of linear analog circuits using sensitivity bands, IEEE Transactions on Circuits and Systems -1: Fundamental Theory and Applications, (47), 1138-1145, 2000.
• [215] Trick T. N., Mayeda W., Sakla A. A., Calculation of parameter values from node voltage measurements, IEEE Transactions on Circuits and Systems, (26), 475-484, 1979.
• [216] Variyam P. N., Chatterjee A., Specification-driven test generation for analog circuits, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (19), 1189-1201,2000.
• [217] Walker A., A step response based mixed-signal BIST approach, Proceedings of the 2001 Southwest Symposium on Mixed-Signal Design, SSMSD'2001, 141-146, 2001.
• [218] Wang P., Yang S., Soft fault test and diagnosis for analog circuits, IEEE International Symposium on Circuits and Systems, ISCAS 2005, (3), 2188-2191, 2005.
• [219] Wang P., Yang S., A new diagnosis approach for handling tolerance in analog and mixed-signal circuits by using fuzzy math', IEEE Transactions on Circuits and Systems -1: Regular Papers, (52), 2118-2126, 2005.
• [220] Wang A., Liu J., Li H., Luan E, Yuan W., A novel algorithm for fault diagnosis of analog circuit with tolerances using improved binary-tree SVMs based on SOMNN clustering, International Conference on Natural Computation, ICNC 2007, (1), 491-496, 2007.
• [221] Wang A., Liu J., Wu J., Zhang X., Researches on soft fault diagnosis algorithm of analogy circuits based on DDAGSVMs, IEEE International Conference on Integration Technology, ICIT'07, 499-503, 2007.
• [222] Wey C. L., Built-in self-test (BIST) structure for analog circuit fault diagnosis, IEEE Transactions on Instrumentation and Measurement, (39), 517-521, 1990.
• [223] Worsman M., Wong M. W. T., Nonlinear circuit fault diagnosis with large change sensitivity, Proceedings of the 1998 IEEE International Conference on Electronics, Circuits and Systems, ICECS 1998, (2), 225-228, 1998.
• [224] Worsman M., Wong M. W. T., Non-linear analog circuit fault diagnosis with large change sensitivity, International Journal of Circuit Theory and Applications, (28), 281-303, 2000.
• [225] Yuan H., Chen G., Shi S., Chen H., Research on fault diagnosis in analog circuit based on wavelet-neural network, Proceedings of the Sixth World Congress on Intelligent Control and Automation, (1), 2659-2662, 2006.
• [226] Zangwill W. I., Garcia V. B., Pathways to solutions, fixed ponts, and quilibria, Prentice-Hall, Englewood Cfills, N. J., 1981.
• [227] Zielinski L., Puchalski B., Rutkowski J., Application of Genetic Algorithms to optimum test point selection with the use of multiple input stimuli, Proceedings of the International Conference on Signals and Electronic Systems, ICSES 2004, 389-392, 2004.
• [228] Zielinski L., Puchalski B., Rutkowski J., Optimum test selection for analog circuits with the use of genetic algorithm, Soft Computing: Methodologies and Applications, Advances in Soft Computing, 129-136, 2005.
• [229] Zielonko R., Królikowski A., Metody pomiarowo diagnostyczne analogowych układów elektronicznych, WNT, Warszawa, 1988.