Chen and Lee Fast DCT Modified Algorithms Implemented in FPGA Chip for Real-Time Image Compression

• Autorzy: Dąbrowska A. , Wiatr K.
• Języki publikacji: EN

Abstrakty

EN

The Discrete Cosine Transform (DCT) is one of the basie varieties of transform coding algorithms. Moreover DCT is used in standard algorithms of compression of still image (JPEG) and video compression of algorithms (MPEG, H.26x). In case of discrete cosine transform of compression 's images of algorithms there are used the blocs: 8x8 pixels. FPGA structures. Authors implemented DCT transform used Chen algorithm and Lee algorithm, because these algorithms most effective for FPGA irnplementation. Paper presents implementations results in Xilinx chips XCV200BG352.

Słowa kluczowe

EN

coding algorithms; implemented algorithm

• Wydawca: Wydawnictwo Politechniki Łódzkiej
• Czasopismo: Journal of Applied Computer Science
• Rocznik: 2005
• Tom: Vol. 13, nr 1
• Strony: 7--16
• Opis fizyczny: Bibliogr. 9 poz.

Twórcy

autor

Dąbrowska A.

• University of Science and Technology, Institute of Electronics, Mickiewicza 30, 30-059 Cracow, Poland
• Academic Computer Center CYFRONETAGH, Nawojki 11, 30-950 Cracow, Poland

autor

Wiatr K.

• University of Science and Technology, Institute of Electronics, Mickiewicza 30, 30-059 Cracow, Poland
• Academic Computer Center CYFRONETAGH, Nawojki 11, 30-950 Cracow, Poland

Bibliografia

• [1] Woods R., Cassidy A., Gray J.: VLSI Architectures for Field Programmable Gate Arrays: A Case Study, www.icspat.com
• [2] Chotin R., Dumonteix Y., Mehrez H.: Use of Redundant Arithmetic on Architecture and Design of a High Performance DCT Macro-block Generator, www.asim.lip6.fr
• [3] Bukhari K., Kuzmanov G., Vassiliadis S.: DCT and IDCT Implementations on Different FPGA Technologies, www.stw.nl
• [4] Heron J., Trainor D., Woods R.: Image Compression Algorithms Using Re-configurable Logic, www.vcc.com
• [5] Trainor D., Heron J., Woods R.: Implementation of the 2D DCT Using a Xilinx XC6264 FPGA, www.ee.qub.ac.uk
• [6] Wiatr K.: Dedicated Hardware Processors for a Real-Time Image Data Pre¬processing Implemented in FPGA Structure. Lecture Notes in Computer Science - No. 1311, Springer-Verlag 1997, vol. II, pp. 69-75
• [7] Wiatr K.: Dedicated System Architecture for Parallel Image Computation used Specialised Hardware Processors Implemented in FPGA Structures. International Journal of Parallel and Distributed Systems and Networks, vol. 1, No. 4, Pittsburgh 1998, pp. 161-168
• [8] Wiatr K., Jamro E.: Implementation of Multipliers in FPGA Structure, Proc. of the IEEE Int. Symp. on Quality Electronic Design, Los Alamitos CA, IEEE Computer Society 2001, pp. 415-420
• [9] Jamro E., Wiatr K.: Dynamic Constant Coefficient Convolvers Implemented in FPGA, Lecture Notes in Computer Science - No. 2438, Springer Verlag 2002, pp. 1110-1113